公开(公告)号：US10103152B2

公开(公告)日：2018-10-16

申请号：US15634066

申请日：2017-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hoon Kim ,  Eun Tae Kim ,  Seong Hun Park ,  Youn Jae Cho ,  Hee Sook Park ,  Woong Hee Sohn ,  Jin Ho Oh

IPC: H01L27/108 ,  H01L21/8242 ,  H01L29/423

Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.

公开(公告)号：US08962438B2

公开(公告)日：2015-02-24

申请号：US14032997

申请日：2013-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghee Park ,  Hideki Horii ,  Hyeyoung Park ,  Jin Ho Oh ,  Hyun-Suk Kwon

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/16 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1293 ,  H01L45/141 ,  H01L45/1683

Abstract: Provided are a variable resistance memory device and a method of forming the same. The variable resistance memory device may include a substrate, a plurality of bottom electrodes on the substrate, and a first interlayer insulating layer including a trench formed therein. The trench exposes the bottom electrodes and extends in a first direction. The variable resistance memory device further includes a top electrode provided on the first interlayer insulating layer and extending in a second direction crossing the first direction and a plurality of variable resistance patterns provided in the trench and having sidewalls aligned with a sidewall of the top electrode.

Abstract translation: 提供了一种可变电阻存储器件及其形成方法。 可变电阻存储器件可以包括衬底，在衬底上的多个底部电极，以及包括形成在其中的沟槽的第一层间绝缘层。 沟槽露出底部电极并沿第一方向延伸。 可变电阻存储器件还包括设置在第一层间绝缘层上并沿与第一方向交叉的第二方向延伸的顶电极和设置在沟槽中并具有与顶电极的侧壁对准的侧壁的多个可变电阻图案。

公开(公告)号：US20150031195A1

公开(公告)日：2015-01-29

申请号：US14297734

申请日：2014-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Tae Kim ,  Jihoon Kim ,  Heesook Park ,  Jin Ho Oh ,  Jongmyeong Lee

IPC: H01L29/49 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device may include conformally forming a gate insulating layer on a substrate having a recess, conformally forming a barrier layer containing fluorine-free tungsten nitride on the substrate with the gate insulating layer using an atomic layer deposition process, and forming a gate electrode on the barrier layer to fill at least a portion of the recess.

Abstract translation: 制造半导体器件的方法可以包括在具有凹部的基板上保形地形成栅极绝缘层，所述栅极绝缘层在基板上使用原子层沉积工艺在栅极绝缘层上保形地形成包含无氟氮化钨的阻挡层，并且形成 在所述阻挡层上的栅电极以填充所述凹部的至少一部分。