公开(公告)号：US09583440B2

公开(公告)日：2017-02-28

申请号：US14792979

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekjung Kim ,  Myung-Ho Kong ,  Heesook Park ,  Youngwook Park ,  Mansug Kang ,  Seonghwee Cheong

IPC: H01L23/48 ,  H01L23/532 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L23/528 ,  H01L27/22 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L23/53266 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/10817 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/228 ,  H01L28/91 ,  H01L29/0642 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device can include a first conductive line crossing over a field isolation region and crossing over an active region of the device, where the first conductive line can include a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and can be configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern.

Abstract translation: 半导体存储器件可以包括在场隔离区域上交叉并穿过器件的有源区的第一导线，其中第一导线可以包括被掺杂的第一导电图案，第二导电图案和金属硅 在第一和第二导电图案之间的氮化物图案，并且可以被配置为在金属 - 氮化硅图案的下边界处提供与第一导电图案的接触，并且被配置为在金属 - 氮化硅图案的上边界处提供扩散阻挡层， 具有第二导电图案的氮化硅图案。

公开(公告)号：US09496223B2

公开(公告)日：2016-11-15

申请号：US15071452

申请日：2016-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Ok Lee ,  Nam-Gun Kim ,  Gyuhwan Oh ,  Heesook Park ,  Hyun-Jung Lee ,  Kyungho Jang

IPC: H01L23/532

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53209 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described.

Abstract translation: 覆盖接触塞的侧壁的间隔件包括相对更受损的第一部分和相对较少受损的第二部分。 间隔物的第一和第二部分的界面与接触塞的金属硅化物层间隔开。 因此，可以提高半导体器件的可靠性。 还描述了相关的制造方法。

公开(公告)号：US10566284B2

公开(公告)日：2020-02-18

申请号：US16027484

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Kwan Kim ,  Sanghoon Ahn ,  Kyu-Hee Han ,  JaeWha Park ,  Heesook Park

IPC: H01L23/532 ,  H01L23/522

Abstract: Provided is a semiconductor device comprising a device region on a substrate, an interlayer dielectric layer on the device region, a first interface layer on a side of the interlayer dielectric layer, a low-k dielectric layer spaced apart from the interlayer dielectric layer across the first interface layer and having a dielectric constant less than that of the interlayer dielectric layer, and a conductive line in the low-k dielectric layer. The first interface layer comprises a first sub-interface layer in contact with the low-k dielectric layer, and a second sub-interface layer in contact with the interlayer dielectric layer. The second sub-interface layer has hydrogen permeability less than that of the first sub-interface layer.

公开(公告)号：US09997591B2

公开(公告)日：2018-06-12

申请号：US15212299

申请日：2016-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-su Lee ,  Gihee Cho ,  Dongkyun Park ,  Hyun-Suk Lee ,  Heesook Park ,  Jongmyeong Lee

IPC: H01L49/02

CPC classification number: H01L28/75

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and capacitor electrically connected to the substrate. The capacitor includes a lower electrode, a dielectric layer disposed on the lower electrode, and an upper electrode disposed on the dielectric layer. The upper electrode includes a first electrode on the dielectric layer and a second electrode on the first electrode, such that the first electrode is disposed between the dielectric layer and the second electrode. The first electrode contains metal oxynitride having a formula of MxOyNz, in which an atomic ratio (y/x) of oxygen (O) to metallic element (M) is a value in the range from 0.5 to 2.

公开(公告)号：US20150031195A1

公开(公告)日：2015-01-29

申请号：US14297734

申请日：2014-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Tae Kim ,  Jihoon Kim ,  Heesook Park ,  Jin Ho Oh ,  Jongmyeong Lee

IPC: H01L29/49 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device may include conformally forming a gate insulating layer on a substrate having a recess, conformally forming a barrier layer containing fluorine-free tungsten nitride on the substrate with the gate insulating layer using an atomic layer deposition process, and forming a gate electrode on the barrier layer to fill at least a portion of the recess.

Abstract translation: 制造半导体器件的方法可以包括在具有凹部的基板上保形地形成栅极绝缘层，所述栅极绝缘层在基板上使用原子层沉积工艺在栅极绝缘层上保形地形成包含无氟氮化钨的阻挡层，并且形成 在所述阻挡层上的栅电极以填充所述凹部的至少一部分。