公开(公告)号：US20240371717A1

公开(公告)日：2024-11-07

申请号：US18409221

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donggon Yoo ,  Sunjung Lee ,  Jeongwon Hwang ,  Myung-Ho Kong ,  Yongho Ha

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a mold layer defining a trench and a conductive structure disposed on the trench. The conductive structure includes a conductive layer and a liner, and the conductive layer includes upper and lower portions. The liner includes a base portion and a sidewall portion on the base portion, and the upper portion of the conductive layer is disposed at a level higher than the sidewall portion of the liner. The sidewall portion of the liner is interposed between the lower portion of the conductive layer and the mold layer, and a top surface of the base portion of the liner is in contact with a bottom surface of the lower portion of the conductive layer. A width of the sidewall portion of the liner may decrease as a level increases.

公开(公告)号：US09583440B2

公开(公告)日：2017-02-28

申请号：US14792979

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekjung Kim ,  Myung-Ho Kong ,  Heesook Park ,  Youngwook Park ,  Mansug Kang ,  Seonghwee Cheong

IPC: H01L23/48 ,  H01L23/532 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L23/528 ,  H01L27/22 ,  H01L49/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L23/53266 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/10817 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/228 ,  H01L28/91 ,  H01L29/0642 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device can include a first conductive line crossing over a field isolation region and crossing over an active region of the device, where the first conductive line can include a first conductive pattern being doped, a second conductive pattern, and a metal-silicon-nitride pattern between the first and second conductive patterns and can be configured to provide a contact at a lower boundary of the metal-silicon-nitride pattern with the first conductive pattern and configured to provide a diffusion barrier at an upper boundary of the metal-silicon-nitride pattern with the second conductive pattern.

Abstract translation: 半导体存储器件可以包括在场隔离区域上交叉并穿过器件的有源区的第一导线，其中第一导线可以包括被掺杂的第一导电图案，第二导电图案和金属硅 在第一和第二导电图案之间的氮化物图案，并且可以被配置为在金属 - 氮化硅图案的下边界处提供与第一导电图案的接触，并且被配置为在金属 - 氮化硅图案的上边界处提供扩散阻挡层， 具有第二导电图案的氮化硅图案。