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    LOW CURRENT PHASE-CHANGE MEMORY DEVICE
    4.
    发明公开
    LOW CURRENT PHASE-CHANGE MEMORY DEVICE 审中-公开

    公开(公告)号：US20230397510A1

    公开(公告)日：2023-12-07

    申请号：US17805707

    申请日：2022-06-07

    Applicant: International Business Machines Corporation

    Inventor： Juntao Li ,  Kangguo Cheng ,  Ruilong Xie ,  Julien Frougier

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L45/126 ,  H01L45/1675 ,  H01L45/1691 ,  H01L45/1616 ,  H01L45/1683 ,  H01L27/2463

    Abstract: A semiconductor structure for a phase-change memory device includes a heater element on a portion of a bottom electrode in a first dielectric material. The semiconductor structure includes a layer of phase-change material that surrounds a portion of a second dielectric material, where the layer of phase-change material forms a three-dimensional shape around the portion of the second dielectric material. A conductive liner is under a first portion of the layer of phase-change material and surrounds a portion of a bottom surface of a hardmask layer and vertical portions of the hardmask layer. A conductive material is on a portion of a top surface of the second dielectric material and abuts the vertical portions of the layer of phase-change material below the conductive liner and the hardmask layer. A top electrode is on a top surface of the conductive material.

    Phase Change Switch Fabricated with Front End of the Line Process
    5.
    发明公开
    Phase Change Switch Fabricated with Front End of the Line Process 审中-公开

    公开(公告)号：US20230389451A1

    公开(公告)日：2023-11-30

    申请号：US17826355

    申请日：2022-05-27

    Applicant: Infineon Technologies AG

    Inventor： Dominik Heiss ,  Matthias Markert

    IPC: H01L45/00

    CPC classification number: H01L45/1226 ,  H01L45/06 ,  H01L45/1286 ,  H01L45/1683

    Abstract: A method includes providing a semiconductor substrate comprising a main surface, forming a dielectric region on the main surface, forming a recess in the dielectric region, forming a strip of phase change material within the recess, forming a heating element that is thermally coupled to the strip of phase change material, forming an interconnection region over the main surface before or after forming the recess, the interconnection region including a metallization layer and a dielectric layer, electrically connecting the strip of phase change material to a connecting one of the metallization layers from the interconnection region, and completing formation of the interconnection region after electrically connecting the strip of phase change material, wherein completing formation of the interconnection region includes forming an outer one of the dielectric layers from the interconnection region that is disposed over the connecting one of the metallization layers and comprises a planar upper surface.

    VERTICAL MEMORY ARCHITECTURE
    8.
    发明公开
    VERTICAL MEMORY ARCHITECTURE 审中-公开

    公开(公告)号：US20230262995A1

    公开(公告)日：2023-08-17

    申请号：US17651217

    申请日：2022-02-15

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1683

    Abstract: Methods, systems, and devices for a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.

    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    9.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20230240086A1

    公开(公告)日：2023-07-27

    申请号：US17857938

    申请日：2022-07-05

    Applicant: SK hynix Inc.

    Inventor： Si Jung YOO ,  Tae Hoon KIM

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L45/143 ,  H01L45/1683

    Abstract: A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a plurality of insulating layers spaced apart from each other in a stacking direction, a slit insulating layer passing through the plurality of insulating layers, a plurality of first variable resistance layers alternately disposed with the plurality of insulating layers in the stacking direction, a plurality of conductive lines interposed between the slit insulating layer and the plurality of first variable resistance layers and alternately disposed with the plurality of insulating layers in the stacking direction, a conductive pillar passing through the plurality of insulating layers and the plurality of first variable resistance layers, and a second variable resistance layer surrounding a sidewall of the conductive pillar.

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