公开(公告)号：US20190198569A1

公开(公告)日：2019-06-27

申请号：US16221385

申请日：2018-12-14

申请人： Fu-Chang Hsu

发明人： Fu-Chang Hsu

IPC分类号： H01L27/24 ,  H01L27/22 ,  H01L45/00

CPC分类号： H01L27/249 ,  H01L27/224 ,  H01L27/2409 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/146 ,  H01L45/1683

摘要： Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a 3D vertical memory array structure is formed by performing operations that include forming an array stack having alternating metal layers and insulator layers, forming a hole through the array stack to expose internal surfaces of the metal layers and internal surfaces of the insulator layers, and performing a metal-oxidation process on the internal surfaces of the metal layers to form selector devices on the internal surfaces of the metal layers. The operations also include depositing one of resistive material or phase-change material within the hole on the selector devices and the internal surfaces of the insulator layers, such that the hole is reduced to a smaller hole, and depositing conductor material in the smaller hole.

公开(公告)号：US20190189688A1

公开(公告)日：2019-06-20

申请号：US15844005

申请日：2017-12-15

申请人： SANDISK TECHNOLOGIES LLC

发明人： Jeffrey S. LILLE

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/249 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608

摘要： A memory cell includes a first electrode which extends horizontally over a substrate, a layer stack containing a phase change memory material layer and a threshold switch material layer which wrap around the first electrode, and a second electrode which contains a first vertical portion and a second vertical portion which extend vertically over the substrate and are located on first and second lateral sides of the layer stack.

公开(公告)号：US20190131523A1

公开(公告)日：2019-05-02

申请号：US16174493

申请日：2018-10-30

申请人： Seoul National University R&DB FOUNDATION

发明人： Byung-Gook Park ,  Sungjun Kim ,  Min-Hwi Kim ,  Tae-Hyeon Kim ,  Sang-Ho Lee

IPC分类号： H01L45/00

CPC分类号： H01L45/1273 ,  H01L27/249 ,  H01L45/04 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

摘要： The present invention relates to a resistance change memory, that is, a resistive memory device. By forming a bottom electrode from a doped semiconductor different material from a conventional one, it is possible to fabricate the memory device simultaneously with peripheral circuit elements. By having one or more electric field concentration regions in the bottom electrode, it is possible to reduce the power consumption reducing the voltage. The present invention can be also stacked vertically in any small and apply to the synaptic device array recently attracting the great interest as the next generation computing technology for realizing the neural imitation system.

公开(公告)号：US20190096481A1

公开(公告)日：2019-03-28

申请号：US15910408

申请日：2018-03-02

申请人： TOSHIBA MEMORY CORPORATION

发明人： Chika TANAKA ,  Masumi SAITOH

IPC分类号： G11C13/00 ,  H01L23/528 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/79 ,  H01L23/528 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1683

摘要： A semiconductor memory device includes a substrate, a stacked body comprising a plurality of first conductors extending in a first direction away from a surface of the substrate and spaced from one another in second and third directions intersecting the first direction and each other, the stacked body having a first region and a second region, a plurality of second conductors extending in the second direction, a plurality of third conductors extending in the third, each third conductor connected to a first end, in the second direction, of a plurality of second conductors in the first region, a plurality of fourth connectors extending in the first direction, each fourth conductor connected to the plurality of second conductors in the second region, and memory cells located between adjacent surfaces of the first and second conductors in the first region.

公开(公告)号：US20180286919A1

公开(公告)日：2018-10-04

申请号：US15671735

申请日：2017-08-08

申请人： Samsung Electronics Co., Ltd.

发明人： Masayuki Terai

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/249 ,  H01L27/2427 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/1683

摘要： A semiconductor device including a data storage pattern is provided. The semiconductor device includes a first conductive line disposed on a substrate and extending in a first direction, a second conductive line disposed on the first conductive line and extending in a second direction, and a first data storage structure and a first selector structure disposed between the first conductive line and the second conductive line and connected in series. The first data storage structure includes a first lower data storage electrode, a first data storage pattern, and a first upper data storage electrode. The first lower data storage electrode includes a first portion facing the first upper data storage electrode and vertically aligned with the first upper data storage electrode. The first data storage pattern includes a first side surface and a second side surface facing each other. The first upper data storage electrode and the first portion of the first lower data storage electrode are disposed to be closer to the first side surface of the first data storage pattern than to the second side surface of the first data storage pattern.

公开(公告)号：US20180277603A1

公开(公告)日：2018-09-27

申请号：US15707042

申请日：2017-09-18

申请人： Toshiba Memory Corporation

发明人： Kenji NAKAMURA ,  Hideyuki NISHIZAWA

IPC分类号： H01L27/28 ,  H01L45/00 ,  H01L51/05 ,  H01L27/24 ,  G11C13/00 ,  H01L51/00

CPC分类号： H01L27/285 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/73 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L51/0058 ,  H01L51/0591

摘要： A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a variable resistance layer disposed between the first conductive layer and the second conductive layer, and an organic molecular layer disposed between the variable resistance layer and the second conductive layer and containing organic molecules. Each of the organic molecules includes a first fused polycyclic unit having a first HOMO level, a second fused polycyclic unit having a second HOMO level higher in energy than the first HOMO level, and a third fused polycyclic unit disposed between the first fused polycyclic unit and the second fused polycyclic unit. The third fused polycyclic unit has a third HOMO level higher in energy than the first HOMO level and the second HOMO level.

公开(公告)号：US20180277598A1

公开(公告)日：2018-09-27

申请号：US15705219

申请日：2017-09-14

申请人： TOSHIBA MEMORY CORPORATION

发明人： Minoru ODA ,  Akira YOTSUMOTO ,  Nobuyuki MOMO ,  Kotaro NODA

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/249 ,  H01L27/2454 ,  H01L45/085 ,  H01L45/1683

摘要： A semiconductor device includes a semiconductor pillar and a control electrode. The semiconductor pillar extends in a first direction, and includes a first region, a second region and an intermediate region provided along the first direction. The intermediate region is positioned between the first region and the second region. The control electrode is disposed at a position so that the control electrode faces the intermediate region via an insulating film. The semiconductor pillar is provided so that a minimum width of the intermediate region in a second direction perpendicular to the first direction is narrower than a first width of the first region in the second direction and a second width of the second region in the second direction.

公开(公告)号：US20180277596A1

公开(公告)日：2018-09-27

申请号：US15468519

申请日：2017-03-24

申请人： SANDISK TECHNOLOGIES LLC

发明人： Yoshio MORI

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L27/11556 ,  H01L27/11582

CPC分类号： H01L27/249 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L45/1233 ,  H01L45/1608

摘要： A three-dimensional memory device includes conductive structures located over a substrate, an alternating stack of insulating layers and electrically conductive layers formed over the conductive structures, and an array of memory structures formed through the alternating stack. Each of the memory structures includes memory elements located at levels of the electrically conductive layers. A contact region can be formed on the alternating stack. Two-stage contact via cavities having a greater width above a top surface of a respective electrically conductive layer and having a narrower width through the alternating stack can be formed in the contact region. Upper insulating spacers and lower insulating spacers are formed such that annular surfaces of the respective electrically conductive layer are physically exposed. Two-stage contact via structures can provide electrical contact between the electrically conductive layers and the conductive structures.

公开(公告)号：US10079268B2

公开(公告)日：2018-09-18

申请号：US15700613

申请日：2017-09-11

申请人： TOSHIBA MEMORY CORPORATION

发明人： Hiroki Okamoto ,  Hiroyuki Kutsukake ,  Akira Hokazono

IPC分类号： G11C5/06 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28

CPC分类号： H01L27/249 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/78 ,  G11C2213/79 ,  H01L21/02271 ,  H01L21/28158 ,  H01L21/32136 ,  H01L27/2454 ,  H01L29/66742 ,  H01L29/78642 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1608

摘要： A memory device includes a first interconnect extending in a first direction, a first and a second semiconductor members extending in a second direction, a first and a second gate lines extending in a third direction, a second and a third interconnects extending in the second direction. The first and the second semiconductor members are arranged along the first direction, with first ends in the second direction connected to the first interconnect. The second interconnect is connected to a second end in the second direction of the first semiconductor member. The third interconnect is connected to a second end in the second direction of the second semiconductor member. The distance between the first interconnect and the first gate line is longer than the distance between the first interconnect and the second gate line.

公开(公告)号：US20180233538A1

公开(公告)日：2018-08-16

申请号：US15693998

申请日：2017-09-01

申请人： TOSHIBA MEMORY CORPORATION

发明人： Tetsu Morooka ,  Takeshi Takagi ,  Takayuki Tsukamoto

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/249 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/71 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675

摘要： A memory device includes a first interconnection extending in a first direction; a second interconnection crossing the first interconnection and extending in a second direction; a resistance change film provided between the first interconnection and the second interconnection, and an intermediate film provided between the second interconnection and the resistance change film. The intermediate film is in contact with the second interconnection, and includes an insulating material.