公开(公告)号：US20230142173A1

公开(公告)日：2023-05-11

申请号：US17519828

申请日：2021-11-05

Applicant: Nantero, Inc.

Inventor： Claude L. Bertin

IPC: G11C13/02 ,  H01L27/28 ,  H01L51/00 ,  H01L51/05

CPC classification number: G11C13/025 ,  H01L27/285 ,  H01L51/0048 ,  H01L51/0591

Abstract: The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.

公开(公告)号：US20170331040A1

公开(公告)日：2017-11-16

申请号：US15528226

申请日：2015-04-29

Applicant: Seoul National University R&DB Foundation

Inventor： Takhee LEE ,  Younggul SONG ,  Jin-Kyun LEE

IPC: H01L51/00 ,  H01L51/10 ,  H01L51/05

CPC classification number: H01L51/0018 ,  H01L21/027 ,  H01L25/046 ,  H01L51/0508 ,  H01L51/0591 ,  H01L51/10

Abstract: A method for manufacturing an organic memory device is disclosed. According to one embodiment, the method comprises the steps of: forming a first electrode on a substrate; forming an organic active layer on the first electrode; and forming a second electrode on the organic active layer through an orthogonal photolithography technique using a fluorinated material.

公开(公告)号：US09685321B2

公开(公告)日：2017-06-20

申请号：US15064735

申请日：2016-03-09

Applicant: Kabushiki Kaisha Toshiba

Inventor： Masaya Terai ,  Shigeki Hattori ,  Hideyuki Nishizawa ,  Koji Asakawa

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  G11C11/56 ,  H01L51/05 ,  H01L27/11582 ,  H01L51/00

CPC classification number: H01L21/02282 ,  G11C11/5664 ,  H01L21/02118 ,  H01L21/28282 ,  H01L27/11582 ,  H01L27/286 ,  H01L51/0077 ,  H01L51/0591

Abstract: A semiconductor memory device in an embodiment includes a semiconductor layer, a control gate electrode, an organic molecular layer provided between the semiconductor layer and the control gate electrode, and a first insulating layer provided between the organic molecular layer and the semiconductor layer, the first insulating layer having a first layer containing alkyl chains and a second layer containing siloxane, the second layer being provided between the first layer and the organic molecular layer.

公开(公告)号：US09614004B2

公开(公告)日：2017-04-04

申请号：US14965660

申请日：2015-12-10

Applicant: Micron Technology, Inc.

Inventor： Kristy A. Campbell

IPC: H01L27/24 ,  B82Y10/00 ,  G11C13/00 ,  H01L29/861 ,  H01L45/00 ,  H01L27/28 ,  H01L51/00

CPC classification number: H01L27/285 ,  B82Y10/00 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/28 ,  H01L27/286 ,  H01L29/8615 ,  H01L45/1608 ,  H01L45/1683 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/0078 ,  H01L51/0591 ,  H01L51/102

Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

公开(公告)号：US09548373B2

公开(公告)日：2017-01-17

申请号：US14842312

申请日：2015-09-01

Applicant: Kabushiki Kaisha Toshiba

Inventor： Shigeki Hattori ,  Tsukasa Tada ,  Masaya Terai ,  Hideyuki Nishizawa ,  Koji Asakawa ,  Yoshiaki Fukuzumi

IPC: H01L29/51 ,  G11C11/56 ,  H01L51/05 ,  H01L51/00 ,  H01L27/28

CPC classification number: H01L29/518 ,  G11C11/5664 ,  G11C16/0483 ,  H01L27/285 ,  H01L29/511 ,  H01L29/517 ,  H01L51/0091 ,  H01L51/0591

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a control gate electrode; and an organic molecular layer, which is provided between the semiconductor layer and the control gate electrode, and has organic molecules including a molecular structure described by a molecular formula (1).

Abstract translation: 根据实施例的非易失性半导体存储器件包括：半导体层; 控制栅电极; 以及设置在半导体层和控制栅电极之间的有机分子层，并且具有包含分子式（1）所示的分子结构的有机分子。

公开(公告)号：US09431100B1

公开(公告)日：2016-08-30

申请号：US14820127

申请日：2015-08-06

Applicant: International Business Machines Corporation

Inventor： Urs T. Duerig ,  Armin W. Knoll ,  Elad Koren ,  Emanuel Loertscher

IPC: G11C13/00 ,  G11C23/00

CPC classification number: G11C13/0014 ,  G11C13/004 ,  G11C13/0069 ,  G11C23/00 ,  G11C2013/0045 ,  G11C2213/35 ,  H01L51/0591

Abstract: A method for storing or switching. The method comprises: arranging a first layer including a first molecular network having a first 2D lattice structure and a second layer including a second molecular network having a second 2D lattice structure at a distance from each other such that the first and the second molecular network interact electronically via molecular orbital interactions, and rotating the first layer relative to the second layer by a rotation angle with a rotation device, wherein an electrical resistance between the first molecular network and the second molecular network changes as a function of the rotation angle, thereby storing information by switching the electrical resistance.

Abstract translation: 一种存储或切换的方法。 该方法包括：布置包括具有第一2D晶格结构的第一分子网络的第一层和包括具有彼此间隔一定距离的第二2D晶格结构的第二分子网络的第二层，使得第一和第二分子网络相互作用 通过分子轨道相互作用电子地转动，并且使第一层相对于第二层旋转与旋转装置的旋转角度，其中第一分子网络和第二分子网络之间的电阻作为旋转角度的函数而改变，由此存储 信息切换电阻。

公开(公告)号：US20160190496A1

公开(公告)日：2016-06-30

申请号：US15061255

申请日：2016-03-04

Applicant: NANTERO INC.

Inventor： Thomas RUECKES ,  H. Montgomery MANNING ,  Rahul SEN, JR.

IPC: H01L51/10 ,  H01L51/00 ,  H01L51/05

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02203 ,  H01L21/02527 ,  H01L21/02606 ,  H01L21/02628 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/1029 ,  H01L29/1606 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1608 ,  H01L51/0003 ,  H01L51/0007 ,  H01L51/0591 ,  H01L51/107 ,  Y10S977/842

Abstract: Methods for passivating a nanotube fabric layer within a nanotube switching device to prevent or otherwise limit the encroachment of an adjacent material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous nanotube fabric layer to fill in the voids within the porous nanotube fabric layer while one or more other material layers are applied adjacent to the nanotube fabric layer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the nanotube fabric layer) is used to form a barrier layer within a nanotube fabric layer. In other embodiments, individual nanotube elements are combined with and nanoscopic particles to limit the porosity of a nanotube fabric layer.

公开(公告)号：US09337423B2

公开(公告)日：2016-05-10

申请号：US14633481

申请日：2015-02-27

Applicant: Nantero Inc.

Inventor： Eliodor G. Ghenciu ,  Thomas Rueckes ,  Thierry Yao ,  J. Thomas Kocab

IPC: H01L29/66 ,  H01L45/00 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/02 ,  H01L51/00 ,  H01L27/24

CPC classification number: H01L51/0591 ,  B82Y10/00 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/009 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/285 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1608 ,  H01L51/0003 ,  H01L51/0045 ,  H01L51/0048 ,  Y10T428/25

Abstract: An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.

Abstract translation: 公开了一种用于在基底上形成复合制品的改进的切换材料。 第一体积的纳米管与第二体积的纳米尺寸颗粒以相对于第一体积纳米管的预定比例组合以形成混合物。 然后可以通过旋涂工艺将该混合物沉积在基材上作为相对较厚的复合制品。 复合制品比具有纳米管的切换制品具有改进的开关性能。 还公开了一种用于形成基本均匀的纳米级碳纳米颗粒的方法，其包含一种或多种同素异形体的碳。

公开(公告)号：US09331291B2

公开(公告)日：2016-05-03

申请号：US14487961

申请日：2014-09-16

Applicant: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION

Inventor： Youngkyoo Kim ,  Sungho Nam ,  Hwajeong Kim ,  Jooyeok Seo ,  Soohyeong Park

IPC: H01L29/08 ,  H01L51/05 ,  G11C13/00 ,  H01L51/00

CPC classification number: H01L51/0591 ,  G11C13/0014 ,  H01L51/0036 ,  H01L51/0529

Abstract: A non-volatile memory device includes a gate electrode, a data storage layer provided on the gate electrode, and a source electrode and a drain electrode provided on the data storage layer and spaced apart from each other. The data storage layer comprises three layers that form hetero-interfaces and have different permittivities from one another.

Abstract translation: 非易失性存储器件包括栅电极，设置在栅电极上的数据存储层，以及设置在数据存储层上并彼此间隔开的源电极和漏电极。 数据存储层包括形成异质界面并且彼此具有不同介电常数的三层。

公开(公告)号：US20160087007A1

公开(公告)日：2016-03-24

申请号：US14965660

申请日：2015-12-10

Applicant: Micron Technology, Inc.

Inventor： Kristy A. Campbell

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/285 ,  B82Y10/00 ,  G11C13/0011 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/28 ,  H01L27/286 ,  H01L29/8615 ,  H01L45/1608 ,  H01L45/1683 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/0078 ,  H01L51/0591 ,  H01L51/102

Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

Abstract translation: 通过在底部电极上提供第一金属 - 硫族化物层来形成具有内置二极管的共轭聚合物层。 随后，第二金属 - 硫族化物层设置在第一金属 - 硫属化物层上并与其接触。 第一金属 - 硫族化物层具有第一导电类型，第二金属 - 硫族化物层具有第二导电类型。 第一和第二金属 - 硫族化物层之间的接触平面形成内置二极管的p-n结。 然后将聚合物层选择性地沉积在第二金属 - 硫族化物层上。 第二金属 - 硫族化物层向聚合物层提供离子以改变其电阻率。 然后在聚合物层上提供顶部电极。 示例性存储单元可以具有以下堆叠结构：第一电极/ n型半导体/ p型半导体/共轭聚合物/第二电极。