公开(公告)号：US12004433B2

公开(公告)日：2024-06-04

申请号：US17810688

申请日：2022-07-05

Applicant: Toshiba Global Commerce Solutions Holdings Corporation

Inventor： Timothy Crockett ,  Lester Bartus, Jr.

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  G11C13/0004 ,  G11C13/0038 ,  H10B63/20 ,  H10N70/231 ,  H10N70/8413 ,  H10N70/8828 ,  G11C2013/009

Abstract: A non-volatile multi-bit storage device that includes a phase change material doped with n-type or p-type semiconductor impurities, a first set of electrodes ohmically coupled to the phase change material, a second set of electrodes configured to apply an electric field across the phase change material. To program the non-volatile multi-bit storage device, an electrical field is applied to the phase change material as crystal annealing cool down is performed. Application of the electric field during the crystal annealing cool down forms a rectified current path through the phase change material.

公开(公告)号：US11672189B2

公开(公告)日：2023-06-06

申请号：US17194609

申请日：2021-03-08

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  John E. Sanchez, Jr. ,  Lawrence Schloss ,  Philip Swab ,  Edmond Ward

IPC: H10N70/20 ,  G11C11/56 ,  G11C13/00 ,  H10N70/00 ,  H10B63/00 ,  G06F30/30 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/08 ,  G06F30/30 ,  G11C11/5685 ,  G11C13/004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0069 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  G11C2013/005 ,  G11C2013/009 ,  G11C2013/0045 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/79

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

公开(公告)号：US20180277207A1

公开(公告)日：2018-09-27

申请号：US15848416

申请日：2017-12-20

Applicant: Toshiba Memory Corporation

Inventor： Yasuhiro NOJIRI

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0038 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0064 ,  G11C13/0069 ,  G11C17/165 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/72 ,  G11C2213/75 ,  H01L27/24 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253

Abstract: A semiconductor device according to an embodiment includes a memory cell array and a drive circuit section. The memory cell array includes memory cells. The drive circuit section adapted to control a driving voltage to be supplied to the memory cells. The memory cells each including a first variable resistance film and a second variable resistance film connected in series to the first variable resistance film. The driving voltage of the second variable resistance film is different from the driving voltage of the first variable resistance film.

公开(公告)号：US20180204617A1

公开(公告)日：2018-07-19

申请号：US15744056

申请日：2015-07-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B Lesartre

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0045 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/77

Abstract: Example implementations relate to writing a desired memory value to a target memory element in a cross-point array of memory elements. For example, a desired memory value for the target memory element may be received, and a sneak current measurement for the target memory element may be received. A first write strength for writing the desired memory value to the target memory element may be determined based on the sneak current measurement.

公开(公告)号：US09899079B2

公开(公告)日：2018-02-20

申请号：US15018726

申请日：2016-02-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Yang Chang ,  Chia-Fu Lee ,  Wen-Ting Chu ,  Yue-Der Chih

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0026 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/16

Abstract: A device is disclosed that includes memory cells, bit lines and a source line. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.

公开(公告)号：US20180025779A1

公开(公告)日：2018-01-25

申请号：US15707724

申请日：2017-09-18

Applicant: Nantero, Inc.

Inventor： Claude L. Bertin ,  Eliodor G. Ghenciu ,  Thomas Rueckes ,  H. Montgomery Manning

IPC: G11C13/00 ,  H01L29/12 ,  G11C13/02 ,  H01L27/115 ,  B82Y10/00 ,  H01L29/06 ,  H01L27/102 ,  H01L51/00 ,  H01L29/861 ,  H01L29/16 ,  G11C11/56 ,  H01L21/822 ,  H01L23/525 ,  H01L27/06 ,  H01L27/12

CPC classification number: G11C13/0097 ,  B82Y10/00 ,  G11C11/56 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/009 ,  G11C2213/19 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/79 ,  H01L21/8221 ,  H01L23/5256 ,  H01L27/0688 ,  H01L27/1021 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/1606 ,  H01L29/861 ,  H01L51/0048 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/80001

Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.

公开(公告)号：US09831287B2

公开(公告)日：2017-11-28

申请号：US15277551

申请日：2016-09-27

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: G11C5/02 ,  H01L27/24 ,  G11C11/56 ,  G11C13/00 ,  H01L45/00 ,  G11C11/34 ,  H01L29/66

CPC classification number: H01L27/2418 ,  G11C5/02 ,  G11C11/34 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/003 ,  G11C2013/009 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2216/08 ,  H01L29/6609 ,  H01L45/00 ,  H01L45/141 ,  H01L45/145 ,  H01L45/16

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

公开(公告)号：US20170309334A1

公开(公告)日：2017-10-26

申请号：US15136414

申请日：2016-04-22

Applicant: Nantero, Inc.

Inventor： Darlene VIVIANI

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/19 ,  G11C2213/35 ,  G11C2213/79 ,  H01L51/0048 ,  H01L51/0575

Abstract: A method for improving the stability of a resistive change cell is disclosed. The stability of a resistive change memory cell-that is, the tendency of the resistive change memory cell to retain its programmed resistive state-may, in certain applications, be compromised if the cell is programmed into an unstable or metastable state. In such applications, a programming method using bursts of sub-pulses within a pulse train is used to drive the resistive change cell material into a stable state during the programming operation, reducing resistance drift over time within the cell.

公开(公告)号：US20170309332A1

公开(公告)日：2017-10-26

申请号：US15138477

申请日：2016-04-26

Applicant: HGST Netherlands B.V.

Inventor： Daniel Bedau

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  H01L23/528

CPC classification number: G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/528 ,  H01L27/2481 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1658

Abstract: To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive random access memory (ReRAM) array is provided. The ReRAM array includes a plurality of memory cells each comprising resistive memory material formed into a layer of a substrate, with resistance properties of the resistive memory material corresponding to data bits stored by the memory cells. The ReRAM array also includes a plurality of interconnect features each comprising conductive material between adjacent memory cells formed into the layer of the substrate, and gate portions coupled onto the memory cells and configured to individually alter the resistance properties of the resistive memory material of associated memory cells responsive to at least voltages applied to the gate portions.

公开(公告)号：US09767902B2

公开(公告)日：2017-09-19

申请号：US15069336

申请日：2016-03-14

Applicant: Nantero Inc.

Inventor： Claude L. Bertin ,  Eliodor G. Ghenciu ,  Thomas Rueckes ,  H. Montgomery Manning

IPC: H01L29/06 ,  G11C13/00 ,  B82Y10/00 ,  G11C11/56 ,  G11C13/02 ,  H01L27/102 ,  H01L29/12 ,  H01L29/16 ,  H01L51/00 ,  H01L27/115 ,  H01L29/861 ,  H01L21/822 ,  H01L23/525 ,  H01L27/06 ,  H01L27/12

CPC classification number: G11C13/0097 ,  B82Y10/00 ,  G11C11/56 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/009 ,  G11C2213/19 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/75 ,  G11C2213/79 ,  H01L21/8221 ,  H01L23/5256 ,  H01L27/0688 ,  H01L27/1021 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/1606 ,  H01L29/861 ,  H01L51/0048 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/80001

Abstract: A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal and a nanoscopic element stack having a plurality of nanoscopic elements arranged in direct electrical contact, a first comprising a nanotube fabric and a second comprising a carbon material, a portion of the nanoscopic element stack in electrical contact with the conductive terminal. Control circuitry is provided in electrical communication with and for applying electrical stimulus to the conductive terminal and to at least a portion of the nanoscopic element stack. At least one of the nanoscopic elements is capable of switching among a plurality of electronic states in response to a corresponding electrical stimuli applied by the control circuitry to the conductive terminal and the portion of the nanoscopic element stack. For each electronic state, the nanoscopic element stack provides an electrical pathway of corresponding resistance.