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    Quantum memory
    2.
    发明授权
    Quantum memory 有权
    量子内存

    公开(公告)号：US08897057B2

    公开(公告)日：2014-11-25

    申请号：US13561843

    申请日：2012-07-30

    申请人： Niklas Adam Bilbo Skold ,  Anthony John Bennett ,  Andrew James Shields

    发明人： Niklas Adam Bilbo Skold ,  Anthony John Bennett ,  Andrew James Shields

    IPC分类号： G11C11/00 ,  G11C11/14

    CPC分类号： G11C11/14 ,  B82Y10/00 ,  G02F1/015 ,  G02F2001/01791 ,  G11C7/005 ,  G11C13/04 ,  G11C2216/08

    摘要： A quantum memory component including a quantum dot molecule having first and second quantum dots provided in respective first and second layers separated by a barrier layer; an exciton comprising an electron and hole bound state in said quantum dot molecule, the spin state of said exciton forming a qubit; first and second electrical contacts respectively provided below the first quantum dot and above the second quantum dot; a voltage source to apply an electric field across said quantum dot molecule; a controller to modulate the electric field across the quantum dot molecule, including an information acquiring circuit to acquire information concerning the relationship between fine structure splitting of the exciton and the applied electric field and a timing circuit to allow switching of the exciton from an indirect configuration to a direct configuration at predetermined times derived from the fine structure splitting.

    摘要翻译： 一种量子存储器组件，包括量子点分子，其具有第一和第二量子点，该第一和第二量子点设置在由阻挡层隔开的相应的第一和第二 在所述量子点分子中包含电子和空穴结合状态的激子，所述激子的自旋状态形成量子位; 分别设置在第一量子点的下方且位于第二量子点的上方的第一和第二电触头; 用于在所述量子点分子上施加电场的电压源; 控制器，用于调制跨越量子点分子的电场，包括信息获取电路以获取关于激子的精细结构分裂与所施加的电场之间的关系的信息，以及定时电路，以允许从间接配置切换激子 以从精细结构分裂得到的预定时间的直接配置。

    Memory Devices, Memory Device Constructions, Constructions, Memory Device Forming Methods, Current Conducting Devices, and Memory Cell Programming Methods
    3.
    发明申请
    Memory Devices, Memory Device Constructions, Constructions, Memory Device Forming Methods, Current Conducting Devices, and Memory Cell Programming Methods 有权
    存储器件，存储器件结构，构造，存储器件形成方法，电流传导器件和存储器单元编程方法

    公开(公告)号：US20120056151A1

    公开(公告)日：2012-03-08

    申请号：US13292932

    申请日：2011-11-09

    申请人： Chandra Mouli

    发明人： Chandra Mouli

    IPC分类号： H01L29/15

    CPC分类号： H01L27/2418 ,  G11C5/02 ,  G11C11/34 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/003 ,  G11C2013/009 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2216/08 ,  H01L29/6609 ,  H01L45/00 ,  H01L45/141 ,  H01L45/145 ,  H01L45/16

    摘要： Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

    摘要翻译： 一些实施例包括具有字线，位线，可选择性地以三种或更多种不同电阻状态中的一种状态配置的存储器元件的存储器件，以及被配置为允许电流从字线通过存储器元件流过到位线的二极管， 电压施加在字线和位线之间，并且如果电压增加或减小则降低电流。 一些实施例包括具有字线，位线，可选择性地以两种或多种不同电阻状态之一配置的存储器元件的存储器件，被配置为阻止第一电流响应于第一电压从位线流向字线的第一二极管，以及 第二二极管，包括电介质材料，并被配置为响应于第二电压允许第二电流从字线流到位线。

    Variable capacitor single-electron transistor including a P-N junction gate electrode
    4.
    发明授权
    Variable capacitor single-electron transistor including a P-N junction gate electrode 有权
    包括P-N结栅电极的可变电容器单电子晶体管

    公开(公告)号：US07619241B2

    公开(公告)日：2009-11-17

    申请号：US11609205

    申请日：2006-12-11

    申请人： Christoph Wasshuber

    发明人： Christoph Wasshuber

    IPC分类号： H01L29/772

    CPC分类号： B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/17 ,  G11C2216/08 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/93 ,  H01L29/94

    摘要： The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

    摘要翻译： 本发明提供单电子晶体管器件100.该器件包括位于衬底115和位于源极和漏极之间的量子级岛120的源极105和漏极110，以在源极和漏极之间形成隧道结125,130 。 该器件还包括位于量子岛120附近的固定栅极电极135.固定栅电极具有与其相关联的电容，该固定栅电极根据施加到固定栅电极的电压的函数而变化。 本发明还包括制造单电子器件300的方法和包括单电子器件810的晶体管电路800。

    Method of manufacturing a memory device
    5.
    发明授权
    Method of manufacturing a memory device 失效
    制造存储器件的方法

    公开(公告)号：US07407856B2

    公开(公告)日：2008-08-05

    申请号：US11296510

    申请日：2005-12-08

    申请人： In-kyeong Yoo ,  Byong-man Kim

    发明人： In-kyeong Yoo ,  Byong-man Kim

    IPC分类号： H01L21/336

    CPC分类号： B82Y10/00 ,  G11C2216/08 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

    摘要： A method of manufacturing a memory device includes defining a field region and an active region in a substrate, forming a field oxide layer on the field region, forming an insulating layer on the active region, patterning the insulating layer to form first and second bit lines separated from and parallel to each other on the active region, forming a memory element for storing data in a nonvolatile state, wherein the memory element passes across the first and second bit lines, and forming a word line on the insulating layer and the memory element.

    摘要翻译： 一种制造存储器件的方法包括在衬底中限定场区域和有源区域，在场区域上形成场氧化物层，在有源区域上形成绝缘层，图案化绝缘层以形成第一和第二位线 形成用于将数据存储在非易失性状态的存储元件，其中存储元件穿过第一和第二位线，并在绝缘层和存储元件上形成字线 。

    Nano-enabled memory devices and anisotropic charge carrying arrays
    6.
    发明授权
    Nano-enabled memory devices and anisotropic charge carrying arrays 有权
    具有纳米功能的存储器件和各向异性带电载体阵列

    公开(公告)号：US07382017B2

    公开(公告)日：2008-06-03

    申请号：US11695728

    申请日：2007-04-03

    申请人： Xiangfeng Duan ,  Calvin Y. H. Cho ,  David L. Heald ,  Chunming Niu ,  J. Wallace Parce ,  David P. Stumbo

    发明人： Xiangfeng Duan ,  Calvin Y. H. Cho ,  David L. Heald ,  Chunming Niu ,  J. Wallace Parce ,  David P. Stumbo

    IPC分类号： H01L29/788

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

    摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

    摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

    Memory device using quantum dots
    7.
    发明申请
    Memory device using quantum dots 有权
    使用量子点的存储器件

    公开(公告)号：US20070221986A1

    公开(公告)日：2007-09-27

    申请号：US11230530

    申请日：2005-09-21

    申请人： Yoon Kang ,  Sang Lee ,  Won Joo

    发明人： Yoon Kang ,  Sang Lee ,  Won Joo

    IPC分类号： H01L29/788

    CPC分类号： H01L27/10 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2216/08 ,  Y10S977/753 ,  Y10S977/783

    摘要： A memory device, which includes a memory layer having quantum dots uniformly dispersed in organic material disposed between an upper electrode layer and a lower electrode layer. The memory device is advantageous because it is nonvolatile and inexpensive, and realizes high integration and high speed switching. Further, size and distribution of the quantum dots may be uniform, thus realizing uniform memory behavior. Furthermore, the memory device is suitable for application to portable electronic devices that must have low power consumption, due to low operating voltages thereof.

    摘要翻译： 一种存储器件，其包括具有均匀分散在设置在上电极层和下电极层之间的有机材料中的量子点的存储层。 存储器件是非易失性且便宜的，因此具有高集成度和高​​速度切换的优点。 此外，量子点的尺寸和分布可以是均匀的，从而实现均匀的记忆行为。 此外，存储器件适用于由于其低工作电压而必须具有低功耗的便携式电子设备。

    Nanocrystal silicon quantum dot memory device
    8.
    发明申请
    Nanocrystal silicon quantum dot memory device 审中-公开
    纳米晶硅量子点存储器件

    公开(公告)号：US20070108502A1

    公开(公告)日：2007-05-17

    申请号：US11281955

    申请日：2005-11-17

    申请人： Tingkai Li ,  Sheng Hsu ,  Lisa Stecker

    发明人： Tingkai Li ,  Sheng Hsu ,  Lisa Stecker

    IPC分类号： H01L29/788 ,  H01L21/336 ,  G11C16/04

    CPC分类号： H01L29/7881 ,  B82Y10/00 ,  G11C16/349 ,  G11C16/3495 ,  G11C2216/08 ,  H01L29/15 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/4925 ,  H01L29/66825

    摘要： A nanocrystal silicon (Si) quantum dot memory device and associated fabrication method have been provided. The method comprises: forming a gate (tunnel) oxide layer overlying a Si substrate active layer; forming a nanocrystal Si memory film overlying the gate oxide layer, including a polycrystalline Si (poly-Si)/Si dioxide stack; forming a control Si oxide layer overlying the nanocrystal Si memory film; forming a gate electrode overlying the control oxide layer; and, forming source/drain regions in the Si active layer. In one aspect, the nanocrystal Si memory film is formed by depositing a layer of amorphous Si (a-Si) using a chemical vapor deposition (CVD) process, and thermally oxidizing a portion of the a-Si layer. Typically, the a-Si deposition and oxidation processes are repeated, forming a plurality of poly-Si/Si dioxide stacks (i.e., 2 to 5 poly-Si/Si dioxide stacks).

    摘要翻译： 已经提供了纳米晶体硅（Si）量子点存储器件和相关的制造方法。 该方法包括：形成覆盖Si衬底有源层的栅极（隧道）氧化层; 形成覆盖栅极氧化物层的纳米晶Si记忆膜，包括多晶Si（多晶硅）/二氧化硅叠层; 形成覆盖在纳米晶Si记忆膜上的对照Si氧化物层; 形成覆盖所述控制氧化物层的栅电极; 并且在Si有源层中形成源/漏区。 在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层（a-Si）并热氧化a-Si层的一部分来形成纳米晶体Si记忆膜。 通常，重复a-Si沉积和氧化过程，形成多个多Si /二氧化硅叠层（即2至5个多硅/二氧化硅叠层）。