公开(公告)号：US07968419B2

公开(公告)日：2011-06-28

申请号：US12234663

申请日：2008-09-21

申请人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

发明人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

IPC分类号： H01L21/20

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

摘要翻译： 提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。 该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。 响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。 通常，响应于Si厚度的增加，阈值和击穿电压都增加。 关于开/关电流比，存在最佳厚度。 该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

公开(公告)号：US07608514B2

公开(公告)日：2009-10-27

申请号：US11900999

申请日：2007-09-15

申请人： Sheng Teng Hsu ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Tingkai Li

IPC分类号： H01L21/336

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.

摘要翻译： 提供金属/半导体/金属（MSM）二进制开关存储器件和制造工艺。 该器件包括存储器电阻器底部电极，存储器电阻器底部电极上方的存储器电阻器材料，以及存储器电阻器材料上的存储器电阻器顶部电极。 MSM底部电极覆盖存储电阻器顶部电极，半导体层覆盖在MSM底部电极上，并且MSM顶部电极覆盖半导体层。 MSM底部电极可以是诸如Pt，Ir，Au，Ag，TiN或Ti的材料。 MSM顶部电极可以是诸如Pt，Ir，Au，TiN，Ti或Al的材料。 半导体层可以是非晶Si，ZnO 2或InO 2。

公开(公告)号：US07585788B2

公开(公告)日：2009-09-08

申请号：US11224549

申请日：2005-09-12

申请人： Wei-Wei Zhuang ,  Yoshi Ono ,  Sheng Teng Hsu ,  Tingkai Li

发明人： Wei-Wei Zhuang ,  Yoshi Ono ,  Sheng Teng Hsu ,  Tingkai Li

IPC分类号： H01L21/31

CPC分类号： H01L21/02156 ,  H01L21/02282 ,  H01L21/316

摘要： A method is provided for forming a rare earth element-doped silicon oxide (SiO2) precursor with nanocrystalline (nc) Si particles. In one aspect the method comprises: mixing Si particles into a first organic solvent, forming a first solution with a first boiling point; filtering the first solution to remove large Si particles; mixing a second organic solvent having a second boiling point, higher than the first boiling point, to the filtered first solution; and, fractionally distilling, forming a second solution of nc Si particles. The Si particles are formed by immersing a Si wafer into a third solution including hydrofluoric (HF) acid and alcohol, applying an electric bias, and forming a porous Si layer overlying the Si wafer. Then, the Si particles are mixed into the organic solvent by depositing the Si wafer into the first organic solvent, and ultrasonically removing the porous Si layer from the Si wafer.

摘要翻译： 提供了一种用于形成具有纳米晶体（nc）Si颗粒的稀土元素掺杂的氧化硅（SiO 2）前体的方法。 一方面，该方法包括：将Si颗粒混合到第一有机溶剂中，形成具有第一沸点的第一溶液; 过滤第一溶液以除去大的Si颗粒; 将具有高于第一沸​​点的第二沸点的第二有机溶剂与过滤的第一溶液混合; 并分馏，形成nc Si颗粒的第二溶液。 通过将Si晶片浸入包括氢氟酸（HF）酸和醇的第三溶液中，施加电偏压并形成覆盖Si晶片的多孔Si层，形成Si颗粒。 然后，通过将Si晶片沉积到第一有机溶剂中，将Si颗粒混入有机溶剂中，并从Si晶片超声波除去多孔Si层。

公开(公告)号：US07544625B2

公开(公告)日：2009-06-09

申请号：US11418273

申请日：2006-05-04

申请人： Pooran Chandra Joshi ,  Tingkai Li ,  Yoshi Ono ,  Apostolos T. Voutsas ,  John W. Hartzell

发明人： Pooran Chandra Joshi ,  Tingkai Li ,  Yoshi Ono ,  Apostolos T. Voutsas ,  John W. Hartzell

IPC分类号： H01L21/31

CPC分类号： H01L21/31608 ,  C23C16/30 ,  C23C16/401 ,  C23C16/402 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0234

摘要： A method is provided for forming a silicon oxide (SiOx) thin-film with embedded nanocrystalline silicon (Si). The method deposits SiOx, where x is in the range of 1 to 2, overlying a substrate, using a high-density (HD) plasma-enhanced chemical vapor deposition (PECVD) process. As a result, the SiOx thin-film is embedded with nanocrystalline Si. The HD PECVD process may use an inductively coupled plasma (ICP) source, a substrate temperature of less than about 400° C., and an oxygen source gas with a silicon precursor. In one aspect, a hydrogen source gas and an inert gas are used, where the ratio of oxygen source gas to inert gas is in the range of about 0.02 to 5. The SiOx thin-film with embedded nanocrystalline Si typically has a refractive index in the range of about 1.6 to 2.2, with an extinction coefficient in the range of 0 to 0.5.

摘要翻译： 提供了一种用嵌入式纳米晶硅（Si）形成氧化硅（SiOx）薄膜的方法。 该方法使用高密度（HD）等离子体增强化学气相沉积（PECVD）工艺沉积SiO x，其中x在1至2的范围内，覆盖在衬底上。 结果，SiO x薄膜埋入有纳米晶体Si。 HD PECVD工艺可以使用电感耦合等离子体（ICP）源，小于约400℃的衬底温度，以及具有硅前体的氧源气体。 一方面，使用氢源气体和惰性气体，其中氧源气体与惰性气体的比例在约0.02至5的范围内。具有嵌入的纳米晶体硅的SiO x薄膜通常具有折射率 约1.6至2.2的范围，消光系数在0至0.5的范围内。

公开(公告)号：US07531207B2

公开(公告)日：2009-05-12

申请号：US10780919

申请日：2004-02-17

申请人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

发明人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

IPC分类号： B05D5/12 ,  C23C16/00

CPC分类号： C23C14/5806 ,  C23C14/086 ,  C23C16/40 ,  C23C16/56

摘要： Methods of forming depositing a ferroelectric thin film, such as PGO, by preparing a substrate with an upper surface of silicon, silicon oxide, or a high-k material, such as hafnium oxide, zirconium oxide, aluminum oxide, and lanthanum oxide, depositing an indium oxide film over the substrate, and then depositing the ferroelectric film using MOCVD.

摘要翻译： 通过制备具有硅，氧化硅或高k材料如氧化铪，氧化锆，氧化铝和氧化镧的上表面的衬底来形成沉积铁电薄膜（例如PGO）的方法，沉积 在衬底上形成氧化铟膜，然后使用MOCVD沉积铁电体膜。

公开(公告)号：US20080280426A1

公开(公告)日：2008-11-13

申请号：US11801210

申请日：2007-05-09

申请人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L29/739 ,  H01L21/20

CPC分类号： C30B29/406 ,  C30B25/183 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02647 ,  H01L29/2003 ,  H01L29/267

摘要： A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. By increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.

摘要翻译： 提供了一种在硅（Si）和氮化镓（GaN）膜之间形成匹配的热膨胀界面的方法。 该方法提供（111）Si衬底并且在压缩覆盖Si衬底上形成第一含铝（Al）的膜。 在第一含Al膜中形成纳米柱孔，其暴露下面的Si衬底的区域。 从暴露区域选择性地生长GaN层，覆盖第一含Al膜。 使用横向纳米外延生长（LNEO）工艺生长GaN。 重复上述过程，在压缩中形成第二含Al膜，在第二含Al膜中形成纳米柱孔，并选择性地生长第二GaN层。 可以最初在低温下生长诸如Al 2 O 3 3，Si 1-x Ge x，InP，GaP，GaAs，AlN，AlGaN或GaN的膜材料。 通过增加生长温度，可以在Si衬底上形成外延GaN的压缩层。

公开(公告)号：US07379320B2

公开(公告)日：2008-05-27

申请号：US11262117

申请日：2005-10-28

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L21/8247

CPC分类号： H01L27/1159 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/11585

摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

摘要翻译： 一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及 沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。 还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

公开(公告)号：US07329548B2

公开(公告)日：2008-02-12

申请号：US11215521

申请日：2005-08-30

申请人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

发明人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

IPC分类号： H01L21/00 ,  H01L21/338 ,  H01L21/8242

CPC分类号： H01L21/28291 ,  H01L29/66583 ,  H01L29/78

摘要： A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.

摘要翻译： 一种制造导电金属氧化物栅极铁电存储晶体管的方法，包括：在衬底上形成氧化物层并去除栅极区域中的氧化物层; 在氧化物层和暴露的栅极区上沉积导电金属氧化物层; 在所述金属氧化物层上沉积钛层; 图案化和蚀刻钛层和金属氧化物层以除去栅极区域之外的基板以除去钛层和金属氧化物层; 沉积，图案化和蚀刻氧化物层以形成栅极沟槽; 沉积和蚀刻阻挡绝缘体层以在栅极沟槽中形成侧壁势垒; 从栅极区域去除钛层; 沉积，平滑和退火栅极沟槽中的铁电层; 沉积，图案化和蚀刻顶部电极; 并完成导电金属氧化物栅极铁电存储晶体管。

公开(公告)号：US07320897B2

公开(公告)日：2008-01-22

申请号：US11090386

申请日：2005-03-23

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Wei-Wei Zhuang

IPC分类号： H01L21/66

CPC分类号： H01L33/08 ,  B82Y20/00 ,  H01L33/18 ,  H01L33/24 ,  H01L33/34 ,  H01L33/502 ,  Y10S977/834

摘要： A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.

摘要翻译： 提供了一种纳米末端电致发光（EL）二极管和一种用于制造所述器件的方法。 该方法包括：形成多个Si纳米二极管; 形成覆盖所述纳米二极管的磷光体层; 并且形成覆盖磷光体层的顶部电极。 纳米二极管通过以下方式形成：形成具有顶表面的Si衬底; 形成Si对孔; 形成层叠Si层的厚度为30〜300纳米（nm）的Si的n +层; 形成覆盖在衬底顶表面上的反应离子蚀刻（RIE）诱导的聚合物草; 使用RIE诱导的聚合物草作为掩模，蚀刻未被掩模覆盖的基底的区域; 以及在由掩模覆盖的衬底的区域中形成纳米二极管二极管。

公开(公告)号：US20070272960A1

公开(公告)日：2007-11-29

申请号：US11890692

申请日：2007-08-07

申请人： Sheng Hsu ,  Tingkai Li

发明人： Sheng Hsu ,  Tingkai Li

IPC分类号： H01L29/76

CPC分类号： G11C11/22 ,  H01L29/40111 ,  H01L29/40114 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391

摘要： The present invention discloses a ferroelectric transistor having a conductive oxide in the place of the gate dielectric. The conductive oxide gate ferroelectric transistor can have a three-layer metal/ferroelectric/metal or a two-layer metal/ferroelectric on top of the conductive oxide gate. By replacing the gate dielectric with a conductive oxide, the bottom gate of the ferroelectric layer is conductive through the conductive oxide to the silicon substrate, thus minimizing the floating gate effect. The memory retention degradation related to the leakage current associated with the charges trapped within the floating gate is eliminated. The fabrication of the ferroelectric transistor by a gate etching process or a replacement gate process is also disclosed.

摘要翻译： 本发明公开了一种具有导电氧化物代替栅电介质的铁电晶体管。 导电氧化物栅极铁电晶体管可以在导电氧化物栅极的顶部上具有三层金属/铁电/金属或两层金属/铁电体。 通过用导电氧化物代替栅极电介质，铁电层的底栅通过导电氧化物导电到硅衬底，从而最小化浮栅效应。 消除了与在浮动栅极内捕获的电荷相关的泄漏电流相关的存储器保持性降低。 还公开了通过栅极蚀刻工艺或替代栅极工艺制造铁电晶体管。