公开(公告)号：US20080026494A1

公开(公告)日：2008-01-31

申请号：US11494181

申请日：2006-07-26

申请人： Wei-Wei Zhuang ,  Yoshi Ono ,  Wei Gao ,  Tingkai Li

发明人： Wei-Wei Zhuang ,  Yoshi Ono ,  Wei Gao ,  Tingkai Li

IPC分类号： H01L21/00

CPC分类号： H05B33/10

摘要： A method of fabricating an electroluminescent device includes preparing a wafer and a doped-silicon oxide precursor solution. The doped-silicon oxide precursor solution is spin coated onto the wafer to form a doped-silicon oxide thin film on the wafer, which is baked at progressively increasing temperatures. The wafer is then rapidly thermally annealed, further annealed in a wet oxygen ambient atmosphere. A transparent top electrode is deposited on the doped-silicon oxide thin film, which is patterned, etched, and annealed. The doped-silicon oxide thin film and the wafer undergo a final annealing step to enhance electroluminescent properties.

摘要翻译： 制造电致发光器件的方法包括制备晶片和掺杂的氧化硅前体溶液。 将掺杂的氧化硅前体溶液旋涂在晶片上以在晶片上形成掺杂的氧化硅薄膜，其在逐渐升高的温度下烘烤。 然后将晶片快速热退火，在湿氧环境气氛中进一步退火。 透明的顶部电极沉积在掺杂的氧化硅薄膜上，其被图案化，蚀刻和退火。 掺杂氧化硅薄膜和晶片进行最终退火步骤以增强电致发光性能。

公开(公告)号：US07323349B2

公开(公告)日：2008-01-29

申请号：US11120385

申请日：2005-05-02

申请人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas J. Tweet ,  Wei-Wei Zhuang

IPC分类号： H01L21/00 ,  H01L21/8242

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1683

摘要： A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.

摘要翻译： 制造电阻器存储器阵列的方法包括制备硅衬底; 在衬底P +层上沉积底部电极，牺牲层和硬掩模层; 掩模，图案化和蚀刻以在第一方向上去除硬掩模，牺牲材料，底部电极的一部分; 沉积一层氧化硅; 掩模，图案化和蚀刻以在垂直于第一方向的第二方向上去除硬掩模，牺牲材料，底部电极的一部分，并且对N +层和至少100nm的硅衬底进行过蚀刻 ; 沉积一层氧化硅; 蚀刻以除去任何剩余的硬掩模和任何剩余的牺牲材料; 沉积一层CMR材料; 沉积顶部电极; 施加光致抗蚀剂，图案化光致抗蚀剂并蚀刻顶部电极; 并将存储器阵列并入集成电路中。

公开(公告)号：US20070238239A1

公开(公告)日：2007-10-11

申请号：US11224549

申请日：2005-09-12

申请人： Wei-Wei Zhuang ,  Yoshi Ono ,  Sheng Teng-Hsu ,  Tingkai Li

发明人： Wei-Wei Zhuang ,  Yoshi Ono ,  Sheng Teng-Hsu ,  Tingkai Li

IPC分类号： H01L21/8238

CPC分类号： H01L21/02156 ,  H01L21/02282 ,  H01L21/316

摘要： A method is provided for forming a rare earth element-doped silicon oxide (SiO2) precursor with nanocrystalline (nc) Si particles. In one aspect the method comprises: mixing Si particles into a first organic solvent, forming a first solution with a first boiling point; filtering the first solution to remove large Si particles; mixing a second organic solvent having a second boiling point, higher than the first boiling point, to the filtered first solution; and, fractionally distilling, forming a second solution of nc Si particles. The Si particles are formed by immersing a Si wafer into a third solution including hydrofluoric (HF) acid and alcohol, applying an electric bias, and forming a porous Si layer overlying the Si wafer. Then, the Si particles are mixed into the organic solvent by depositing the Si wafer into the first organic solvent, and ultrasonically removing the porous Si layer from the Si wafer.

摘要翻译： 提供了用纳米晶体（nc）Si颗粒形成稀土元素掺杂的氧化硅（SiO 2）前体的方法。 一方面，该方法包括：将Si颗粒混合到第一有机溶剂中，形成具有第一沸点的第一溶液; 过滤第一溶液以除去大的Si颗粒; 将具有高于第一沸​​点的第二沸点的第二有机溶剂与过滤的第一溶液混合; 并分馏，形成nc Si颗粒的第二溶液。 通过将Si晶片浸入包括氢氟酸（HF）酸和醇的第三溶液中，施加电偏压并形成覆盖Si晶片的多孔Si层，形成Si颗粒。 然后，通过将Si晶片沉积到第一有机溶剂中，将Si颗粒混入有机溶剂中，并从Si晶片超声波除去多孔Si层。

公开(公告)号：US07235407B2

公开(公告)日：2007-06-26

申请号：US10855942

申请日：2004-05-27

申请人： Tingkai Li ,  Lawrence J. Charneski ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Lawrence J. Charneski ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1616

摘要： A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and, forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.

摘要翻译： 提供了多层Pr 1 x 1 x x MnO 3（PCMO）薄膜电容器和相关的沉积方法，用于形成双极开关 薄膜。 该方法包括：形成底部电极; 沉积纳米晶体PCMO层; 沉积多晶的PCMO层; 形成具有双极开关特性的多层PCMO膜; 并且形成覆盖PCMO膜的顶部电极。 如果多晶层沉积在纳米晶层之上，则可以用窄脉冲宽度，负电压脉冲写入高电阻。 PCMO膜可以使用窄脉冲宽度，正幅度脉冲复位为低电阻。 同样，如果纳米晶层沉积在多晶层上，则可以用窄脉冲宽度，正电压脉冲写入高电阻，并使用窄脉冲宽度，负幅度脉冲将其复位为低电阻。

公开(公告)号：US07214583B2

公开(公告)日：2007-05-08

申请号：US11130983

申请日：2005-05-16

申请人： Sheng Teng Hsu ,  Tingkai Li ,  David R. Evans ,  Wei-Wei Zhuang ,  Wei Pan

发明人： Sheng Teng Hsu ,  Tingkai Li ,  David R. Evans ,  Wei-Wei Zhuang ,  Wei Pan

IPC分类号： H01L21/8242

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1625

摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.

摘要翻译： 提供了非对称结构的存储单元和制造方法。 该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。 在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度 的第一层。 在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

公开(公告)号：US07193267B2

公开(公告)日：2007-03-20

申请号：US10971204

申请日：2004-10-21

申请人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： H01L29/76

CPC分类号： G11C11/15 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  H01L27/24

摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.

摘要翻译： 提供了电阻式交叉点存储器件，以及制造和使用方法。 存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。 在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 在电阻性存储器材料和下电极之间的界面处形成二极管，其可以形成为掺杂区域。 电阻性交叉点存储器件通过在衬底内掺杂一个极性而形成，然后将相反极性的线的掺杂区域形成二极管。 然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。 然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

公开(公告)号：US07166485B1

公开(公告)日：2007-01-23

申请号：US11175797

申请日：2005-07-05

申请人： Tingkai Li ,  Sheng Teng Hsu ,  Wei-Wei Zhuang

发明人： Tingkai Li ,  Sheng Teng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L21/00 ,  H01L29/06

CPC分类号： H01L33/34 ,  B82Y20/00 ,  H01L33/0012

摘要： A superlattice nanocrystal Si—SiO2 electroluminescence (EL) device and fabrication method have been provided. The method comprises: providing a Si substrate; forming an initial SiO2 layer overlying the Si substrate; forming an initial polysilicon layer overlying the initial SiO2 layer; forming SiO2 layer overlying the initial polysilicon layer; repeating the polysilicon and SiO2 layer formation, forming a superlattice; doping the superlattice with a rare earth element; depositing an electrode overlying the doped superlattice; and, forming an EL device. In one aspect, the polysilicon layers are formed by using a chemical vapor deposition (CVD) process to deposit an amorphous silicon layer, and annealing. Alternately, a DC-sputtering process deposits each amorphous silicon layer, and following the forming of the superlattice, polysilicon is formed by annealing the amorphous silicon layers. Silicon dioxide can be formed by either thermal annealing or by deposition using a DC-sputtering process.

摘要翻译： 已经提供了超晶格纳米晶Si-SiO 2电致发光（EL）器件及其制造方法。 该方法包括：提供Si衬底; 形成覆盖Si衬底的初始SiO 2层; 形成覆盖初始SiO 2层的初始多晶硅层; 形成覆盖初始多晶硅层的SiO 2层; 重复多晶硅和SiO 2层形成，形成超晶格; 用稀土元素掺杂超晶格; 沉积覆盖掺杂超晶格的电极; 并且形成EL器件。 在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层和退火来形成多晶硅层。 或者，DC溅射工艺沉积每个非晶硅层，并且在形成超晶格之后，通过退火非晶硅层形成多晶硅。 可以通过热退火或通过使用DC溅射工艺的沉积来形成二氧化硅。

公开(公告)号：US20070015329A1

公开(公告)日：2007-01-18

申请号：US11216398

申请日：2005-08-31

申请人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang ,  David Evans

发明人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang ,  David Evans

IPC分类号： H01L21/8242

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

摘要翻译： 提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。 该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。 可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

公开(公告)号：US20070010037A1

公开(公告)日：2007-01-11

申请号：US11175797

申请日：2005-07-05

申请人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang

发明人： Tingkai Li ,  Sheng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L21/00

CPC分类号： H01L33/34 ,  B82Y20/00 ,  H01L33/0012

摘要： A superlattice nanocrystal Si—SiO2 electroluminescence (EL) device and fabrication method have been provided. The method comprises: providing a Si substrate; forming an initial SiO2 layer overlying the Si substrate; forming an initial polysilicon layer overlying the initial SiO2 layer; forming SiO2 layer overlying the initial polysilicon layer; repeating the polysilicon and SiO2 layer formation, forming a superlattice; doping the superlattice with a rare earth element; depositing an electrode overlying the doped superlattice; and, forming an EL device. In one aspect, the polysilicon layers are formed by using a chemical vapor deposition (CVD) process to deposit an amorphous silicon layer, and annealing. Alternately, a DC-sputtering process deposits each amorphous silicon layer, and following the forming of the superlattice, polysilicon is formed by annealing the amorphous silicon layers. Silicon dioxide can be formed by either thermal annealing or by deposition using a DC-sputtering process.

摘要翻译： 已经提供了超晶格纳米晶Si-SiO 2电致发光（EL）器件及其制造方法。 该方法包括：提供Si衬底; 形成覆盖Si衬底的初始SiO 2层; 形成覆盖初始SiO 2层的初始多晶硅层; 形成覆盖在初始多晶硅层上的SiO 2层; 重复多晶硅和SiO 2层形成，形成超晶格; 用稀土元素掺杂超晶格; 沉积覆盖掺杂超晶格的电极; 并且形成EL器件。 在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层和退火来形成多晶硅层。 或者，DC溅射工艺沉积每个非晶硅层，并且在形成超晶格之后，通过退火非晶硅层形成多晶硅。 可以通过热退火或通过使用DC溅射工艺的沉积来形成二氧化硅。

公开(公告)号：US07029924B2

公开(公告)日：2006-04-18

申请号：US10755654

申请日：2004-01-12

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

IPC分类号： H01L21/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7-X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1-XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

摘要翻译： 提供了一种用于形成缓冲层存储单元的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。 在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。 顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域 和0.6，厚度在10至200nm的范围内。