公开(公告)号：US20240170059A1

公开(公告)日：2024-05-23

申请号：US18191668

申请日：2023-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  NATIONAL TAIWAN UNIVERSITY ,  National Taiwan Normal University

Inventor： Kuo-Yu HSIANG ,  Min-Hung LEE

IPC: G11C13/00

CPC classification number: G11C13/0038 ,  G11C13/0035 ,  G11C2213/31

Abstract: A method of operating a memory cell includes the following steps. A first plurality of bias operations is performed to the memory cell using a first voltage, wherein the memory cell comprises a variable resistance pattern, and the first voltage of each cycle of the first plurality of bias operations has a same first polarity. The memory cell is determined whether reaches a fatigue threshold. After the determination determines that the memory cell reaches the fatigue threshold, a second plurality of bias operations is performed to the memory cell using a second voltage, wherein the second voltage of each cycle of the second plurality of bias operations has a same second polarity, and the second polarity is opposite to the first polarity.

公开(公告)号：US20240138275A1

公开(公告)日：2024-04-25

申请号：US18048594

申请日：2022-10-20

Applicant: CYBERSWARM, INC.

Inventor： Viorel-Georgel Dumitru ,  Octavian-Narcis Ionescu

IPC: H01L45/00 ,  G11C11/56 ,  G11C13/00

CPC classification number: H01L45/147 ,  G11C11/5685 ,  G11C13/004 ,  G11C13/0069 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/1625 ,  G11C2213/15 ,  G11C2213/31

Abstract: One or more embodiments disclosed herein describe a nonvolatile, analog programmable resistive memory with a plurality of memory states. The programmable resistive memory includes a substrate, an IGZO resistive layer and electrical contacts. The electrical contacts are deposited on the IGZO layer, in the same plane. The electrical contacts may have various shapes in order to obtain spatially variable distances between the electrical contacts. The resistance of the resistive memory can be brought from an initial low value to a plurality of various higher values by applying electrical voltage pulses with various durations and various amplitudes and/or by applying one or more DC voltage sweeps. Also, the high voltage limit during the DC voltage sweeps could be set at values ranging from few volts to few tens of volts. In this manner, the IGZO programmable resistive memory could be set in a plurality of memory states.

公开(公告)号：US11923289B2

公开(公告)日：2024-03-05

申请号：US17837923

申请日：2022-06-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  G11C13/00 ,  H01L23/528 ,  H01L27/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B63/00 ,  H10N70/00

CPC classification number: H01L23/52 ,  G11C13/0007 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35 ,  H10B63/845 ,  H10N70/8822 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8833 ,  H10N70/8836 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L2924/0002 ,  H10B41/35 ,  H10N70/882 ,  H10N70/883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

公开(公告)号：US20190088324A1

公开(公告)日：2019-03-21

申请号：US15911413

申请日：2018-03-05

Applicant: Toshiba Memory Corporation

Inventor： Kensuke OTA ,  Masamichi Suzuki ,  Reika Ichihara

IPC: G11C13/00 ,  G11C7/18

CPC classification number: G11C13/0007 ,  G11C7/18 ,  G11C11/5685 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0057 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/54 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/77

Abstract: According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.

公开(公告)号：US10003020B2

公开(公告)日：2018-06-19

申请号：US15367902

申请日：2016-12-02

Applicant: 4D-S PTY, LTD

Inventor： Dongmin Chen

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00 ,  G11C11/56

CPC classification number: H01L45/1233 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/77 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1625 ,  H01L45/1633

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

公开(公告)号：US20180017870A1

公开(公告)日：2018-01-18

申请号：US15547105

申请日：2015-04-27

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Ning GE ,  Zhiyong LI ,  Jianhua Yang ,  R. Stanley Williams

IPC: G03F7/16 ,  H01L27/24 ,  G11C19/28 ,  H01L45/00 ,  G11C13/00

CPC classification number: G03F7/16 ,  B41J2/04541 ,  B41J2/04543 ,  B41J2/0458 ,  B41J2/14129 ,  B41J2202/13 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C19/28 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/10817 ,  H01L27/2436 ,  H01L27/2463 ,  H01L28/87 ,  H01L28/91 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

Abstract: An integrated circuit may include a substrate with a plurality of transistors formed in the substrate. The plurality of transistors may be coupled to a first metal layer formed over the plurality of transistors. A plurality of high dielectric nanometer capacitors may be formed of memristor switch material between the first metal layer and a second metal layer formed over the plurality of high dielectric capacitors. The plurality of high dielectric capacitors may operate as memory storage cells in dynamic logic.

公开(公告)号：US09837149B2

公开(公告)日：2017-12-05

申请号：US15181009

申请日：2016-06-13

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Bruce Lynn Bateman ,  Christophe Chevallier ,  Darrell Rinerson ,  Chang Hua Siau

IPC: G11C17/00 ,  G11C13/00 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C13/004 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/77

Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

公开(公告)号：US09831425B2

公开(公告)日：2017-11-28

申请号：US14844805

申请日：2015-09-03

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  John E. Sanchez, Jr. ,  Lawrence Schloss ,  Philip Swab ,  Edmond Ward

IPC: H01L45/00 ,  G06F17/50 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/08 ,  G06F17/5045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/005 ,  G11C2013/009 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625

Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

公开(公告)号：US20170323929A1

公开(公告)日：2017-11-09

申请号：US15521352

申请日：2014-10-31

Applicant: Nokia Technologies Oy

Inventor： Alexander Alexandrovich BESSONOV ,  Michael ASTLEY

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L27/2409 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/35 ,  G11C2213/72 ,  G11C2213/73 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1641

Abstract: In accordance with an example embodiment of the present invention, an apparatus is disclosed. The apparatus includes a resistive memory component including an active material and two or more electrodes in electrical contact with the active material of the resistive memory component; and a selector component providing control over the resistive memory component, the selector component including an active material and two or more electrodes in electrical contact with the active material of the selector component. The resistive memory component and the selector component share one or more electrodes, and the resistive memory component and the selector component share at least part of the active material. A method and apparatus for producing the apparatus are also disclosed.

公开(公告)号：US20170256312A1

公开(公告)日：2017-09-07

申请号：US15265067

申请日：2016-09-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kikuko SUGIMAE ,  Yusuke ARAYASHIKI

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/71 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.