公开(公告)号：US11996146B2

公开(公告)日：2024-05-28

申请号：US17599528

申请日：2020-04-02

申请人： Jun-sung Kim

发明人： Jun-sung Kim

IPC分类号： G11C11/00 ,  G06N3/063 ,  G11C13/00

CPC分类号： G11C13/004 ,  G06N3/063 ,  G11C13/003 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/71

摘要： The present invention provides a method for reading a current for processing analog information in a memory array for a synaptic device. To this end, the present invention provides a method for reading a memory array including a two-terminal switching material, including (a) selecting at least one cell by applying a voltage to the memory array and (b) simultaneously measuring the sum of currents from the at least one cell selected. The voltage applied to the at least one cell selected in operation (a) is higher than a voltage applied to at least one cell not selected while being within a range in which all of the selected at least one cell is not turned on.

公开(公告)号：US11923289B2

公开(公告)日：2024-03-05

申请号：US17837923

申请日：2022-06-10

申请人： Micron Technology, Inc.

发明人： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC分类号： H01L23/52 ,  G11C13/00 ,  H01L23/528 ,  H01L27/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B63/00 ,  H10N70/00

CPC分类号： H01L23/52 ,  G11C13/0007 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35 ,  H10B63/845 ,  H10N70/8822 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8833 ,  H10N70/8836 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L2924/0002 ,  H10B41/35 ,  H10N70/882 ,  H10N70/883 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

公开(公告)号：US11804263B2

公开(公告)日：2023-10-31

申请号：US17365306

申请日：2021-07-01

申请人： SK hynix Inc.

发明人： Tae Jung Ha

IPC分类号： G11C11/56 ,  G11C13/00 ,  H10N70/20 ,  H10N70/00

CPC分类号： G11C11/5685 ,  G11C13/004 ,  G11C13/0007 ,  G11C13/0069 ,  H10N70/24 ,  H10N70/8833 ,  G11C2213/32

摘要： A semiconductor device may include a word line, a bit line crossing the word line, and a memory cell coupled to the word line and the bit line to receive an electrical signal to control the memory cell and including a switching material layer and an oxidation-reduction reversible material layer that is in contact with the switching material layer to allow for either oxidation reaction or reduction reaction to occur in response to different amplitudes and different polarities of the electrical signal, wherein the oxidation-reduction reversible material layer and the switching material layer responds to a first threshold voltage and a first polarity of the electrical signal to generate an oxidation interface between the switching material layer and the oxidation-reduction reversible material layer, and responds to a second threshold voltage and a second polarity of the electrical signal to reduce the generation of the oxidation interface.

公开(公告)号：US20190088324A1

公开(公告)日：2019-03-21

申请号：US15911413

申请日：2018-03-05

申请人： Toshiba Memory Corporation

发明人： Kensuke OTA ,  Masamichi Suzuki ,  Reika Ichihara

IPC分类号： G11C13/00 ,  G11C7/18

CPC分类号： G11C13/0007 ,  G11C7/18 ,  G11C11/5685 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0057 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/54 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/77

摘要： According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.

公开(公告)号：US20190027219A1

公开(公告)日：2019-01-24

申请号：US16138673

申请日：2018-09-21

申请人： Crossbar, Inc.

发明人： Hagop Nazarian ,  Sung Hyun Jo

IPC分类号： G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： G11C13/0069 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/11 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/79

摘要： A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch.

公开(公告)号：US20180350880A1

公开(公告)日：2018-12-06

申请号：US15777535

申请日：2015-12-23

申请人： INTEL CORPORATION

发明人： PRASHANT MAJHI ,  ELIJAH V. KARPOV ,  RAVI PILLARISETTY ,  UDAY SHAH ,  NILOY MUKHERJEE

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16

CPC分类号： H01L27/2481 ,  G11C11/161 ,  G11C11/165 ,  G11C13/0021 ,  G11C2213/32 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L45/08 ,  H01L45/141 ,  H01L45/146

摘要： A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfOx), tantalum oxide (TaOx), or titanium dioxide (TiOx), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.

公开(公告)号：US20180277760A1

公开(公告)日：2018-09-27

申请号：US15927635

申请日：2018-03-21

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  UNIVERSITE D'AIX-MARSEILLE ,  CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)

发明人： Alexis KRAKOVINSKY ,  Marc BOCQUET ,  Jean COIGNUS ,  Vincenzo DELLA MARCA ,  Jean-Michel PORTAL ,  Romain WACQUEZ

IPC分类号： H01L45/00 ,  G11C13/00 ,  H01L21/66 ,  H01L27/24

CPC分类号： H01L45/1641 ,  G11C7/005 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/04 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/52 ,  H01L22/20 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

摘要： A method for forming a non-volatile memory cell intended to switch the memory cell from an unformed state to a formed state, the memory cell including an ordered stack of a lower electrode, a layer of insulating material and an upper electrode. The forming method includes a breakdown operation in which at least one laser shot is emitted towards the layer of insulating material to make the layer of insulating material active by making it pass from a high resistance state to a low resistance state, the memory cell being formed when the layer of insulating material is active.

公开(公告)号：US10074694B2

公开(公告)日：2018-09-11

申请号：US15017899

申请日：2016-02-08

申请人： Toshiba Memory Corporation

发明人： Takeshi Takagi ,  Takeshi Yamaguchi ,  Masaki Yamato ,  Hiroyuki Ode ,  Toshiharu Tanaka

IPC分类号： H01L27/24 ,  H01L45/00 ,  G11C13/00

CPC分类号： H01L27/249 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0033 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/77 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16

摘要： According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.

公开(公告)号：US20180254414A1

公开(公告)日：2018-09-06

申请号：US15878036

申请日：2018-01-23

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS (CROLLES 2) SAS

发明人： Sophie BERNASCONI ,  Christelle Charpin-Nicolle ,  Aomar Halimaoui

IPC分类号： H01L45/00 ,  G11C13/00

CPC分类号： H01L45/10 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/56 ,  H01L21/02258 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1641

摘要： The present invention relates to a memory device comprising a first electrode (27), a second electrode (28) and an active portion that can change conductive state, positioned between a first face of the first electrode (27) and a first face of the second electrode (28).The first electrode (27) comprises an upper portion forming the first face of the first electrode (27). At least one out of the upper portion and the active portion that can change conductive state comprises a porous layer (15).

公开(公告)号：US10003020B2

公开(公告)日：2018-06-19

申请号：US15367902

申请日：2016-12-02

申请人： 4D-S PTY, LTD

发明人： Dongmin Chen

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00 ,  G11C11/56

CPC分类号： H01L45/1233 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/77 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1625 ,  H01L45/1633

摘要： A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.