公开(公告)号：US20160359108A1

公开(公告)日：2016-12-08

申请号：US15117594

申请日：2014-03-25

申请人： INTEL CORPORATION

发明人： PRASHANT MAJHI ,  ELIJAH V. KARPOV ,  UDAY SHAH ,  NILOY MUKHERJEE ,  CHARLES C. KUO ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  ROBERT S. CHAU

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/08 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1683

摘要： Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

摘要翻译： 公开了用于形成诸如非平面电阻随机存取存储器（ReRAM或RRAM）单元的非平面电阻存储器单元的技术。 该技术可以用于相对于给定存储器单元空间的平面电阻存储器单元来减少所形成的电压要求和/或电阻（例如在低电阻状态期间的电阻）。 非平面电阻式存储单元包括第一电极，第二电极和设置在第一和第二电极之间的开关层。 在形成非平面电阻式存储单元之后，第二电极可以基本上位于开关层的相对部分之间，并且第一电极可以基本上与开关层的至少两侧相邻。 在一些情况下，氧交换层（OEL）可以设置在开关层与第一和第二电极中的一个之间，以例如增加在电池中引入材料的灵活性。

公开(公告)号：US20180350880A1

公开(公告)日：2018-12-06

申请号：US15777535

申请日：2015-12-23

申请人： INTEL CORPORATION

发明人： PRASHANT MAJHI ,  ELIJAH V. KARPOV ,  RAVI PILLARISETTY ,  UDAY SHAH ,  NILOY MUKHERJEE

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16

CPC分类号： H01L27/2481 ,  G11C11/161 ,  G11C11/165 ,  G11C13/0021 ,  G11C2213/32 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L45/08 ,  H01L45/141 ,  H01L45/146

摘要： A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfOx), tantalum oxide (TaOx), or titanium dioxide (TiOx), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.

公开(公告)号：US20170148982A1

公开(公告)日：2017-05-25

申请号：US15126138

申请日：2014-06-26

申请人： INTEL CORPORATION

发明人： ELIJAH V. KARPOV ,  PRASHANT MAJHI ,  RAVI PILLARISETTY ,  BRIAN S. DOYLE ,  NILOY MUKHERJEE ,  UDAY SHAH ,  ROBERT S. CHAU

IPC分类号： H01L45/00

CPC分类号： H01L45/1206 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： Oxide-based three-terminal resistive switching logic devices and methods of fabricating oxide-based three-terminal resistive switching logic devices are described. In a first example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes an active oxide material region disposed directly between a metal source region and a metal drain region. The device also includes a gate electrode disposed above the active oxide material region. In a second example, a three-terminal resistive switching logic device includes an active region disposed above a substrate. The active region includes a first active oxide material region spaced apart from a second oxide material region. The device also includes metal input regions disposed on either side of the first and second active oxide material regions. A metal output region is disposed between the first and second active oxide material regions.