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公开(公告)号：US10446552B2
公开(公告)日：2019-10-15
申请号：US15912664
申请日：2018-03-06
发明人： Dandan Zhao , Reika Ichihara , Haruka Sakuma , Yuuichiro Mitani
IPC分类号： H01L27/10 , G11C13/00 , H01L27/105 , H01L45/00
摘要： According to one embodiment, a memory element includes a first conductive layer, a second conductive layer, and a first layer. The first conductive layer includes an ion source. The first layer includes a first element and is provided between the first conductive layer and the second conductive layer. An electronegativity of the first element is greater than 2. The first layer includes a first region and a second region. The first region includes the first element. The second region is provided between the first region and the second conductive layer. The second region does not include the first element, or the second region includes the first element, and a concentration of the first element in the first region is higher than a concentration of the first element in the second region.
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公开(公告)号：US10446227B2
公开(公告)日：2019-10-15
申请号：US15911413
申请日：2018-03-05
发明人： Kensuke Ota , Masamichi Suzuki , Reika Ichihara
摘要： According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.
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公开(公告)号：US20190088324A1
公开(公告)日：2019-03-21
申请号：US15911413
申请日：2018-03-05
发明人： Kensuke OTA , Masamichi Suzuki , Reika Ichihara
CPC分类号： G11C13/0007 , G11C7/18 , G11C11/5685 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0057 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/51 , G11C2213/54 , G11C2213/72 , G11C2213/76 , G11C2213/77
摘要： According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.
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公开(公告)号：US09928908B2
公开(公告)日：2018-03-27
申请号：US15425388
申请日：2017-02-06
CPC分类号： G11C13/0069 , G11C11/5614 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0097 , G11C2013/005 , G11C2013/0073 , G11C2013/009 , G11C2013/0092 , G11C2213/15 , G11C2213/33 , H01L27/101 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/148
摘要： According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.
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公开(公告)号：US09779808B2
公开(公告)日：2017-10-03
申请号：US15262575
申请日：2016-09-12
CPC分类号： G11C13/004 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2013/0092 , G11C2213/33 , G11C2213/34 , G11C2213/71 , H01L27/2481 , H01L27/249 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146
摘要： A resistance random access memory device includes a control circuit. The control circuit applies a first voltage between the plurality of second interconnects and one of the first interconnects for a first time when switching resistance states of the variable resistance members from a first state to a second state, and the control circuit applies a second voltage between the plurality of second interconnects and the one of the first interconnects for a second time after applying the first voltage when the resistance state of one or more of the variable resistance members of a plurality of the variable resistance members connected to the one of the first interconnects is in the first state. The second voltage has the same polarity as the first voltage and is lower than the first voltage. The second time is longer than the first time.
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