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    Methods for fabricating programmable devices and related structures
    7.
    发明授权
    Methods for fabricating programmable devices and related structures 有权
    制造可编程器件和相关结构的方法

    公开(公告)号：US09564447B1

    公开(公告)日：2017-02-07

    申请号：US14842345

    申请日：2015-09-01

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Suraj K. Patil ,  Ajey P. Jacob ,  Min-hwa Chi

    IPC分类号： H01L27/112 ,  G11C13/00

    CPC分类号： H01L27/11206 ,  G11C13/0002 ,  G11C13/0009 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/008 ,  H01L23/5256 ,  H01L23/53276 ,  H01L27/112 ,  H01L29/0676 ,  H01L29/413

    摘要： Methods and structures for programmable device fabrication are provided. The methods for fabricating a programmable device include, for example forming at least one via opening in a layer of the programmable device and providing a catalyzing material over a lower surface of the at least one via opening; forming a plurality of nanowires or nanotubes in the at least one via opening using the catalyzing material as a catalyst for the forming of the plurality of nanowires or nanotubes; and providing a dielectric material in the at least one via opening so that the dielectric material surrounds the plurality of nanowires or nanotubes. The programmable device may, in subsequent or separate programming steps, have programming of the programmable device made permanent via thermal oxidation of the dielectric material and the plurality of nanowires or nanotubes, leaving a non-conducting material behind in the at least one via opening.

    摘要翻译： 提供了可编程器件制造的方法和结构。 制造可编程装置的方法包括例如在可编程装置的层中形成至少一个通孔，并在至少一个通孔开口的下表面上提供催化材料; 在所述至少一个通孔开口中使用所述催化材料形成多个纳米线或纳米管作为用于形成所述多个纳米线或纳米管的催化剂; 以及在所述至少一个通孔开口中提供介电材料，使得所述电介质材料包围所述多个纳米线或纳米管。 可编程设备在随后或单独的编程步骤中可以通过介电材料和多个纳米线或纳米管的热氧化使可编程器件的编程永久化，在至少一个通孔开口之后留下非导电材料。

    ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY UNIT THAT INCLUDES CELL MATS OF A PLURALITY OF PLANES VERTICALLY STACKED
    10.
    发明申请
    ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY UNIT THAT INCLUDES CELL MATS OF A PLURALITY OF PLANES VERTICALLY STACKED 有权
    电子设备，包括一个半导体存储单元，其中包括垂直堆叠的多个平面图的单元格

    公开(公告)号：US20160197036A1

    公开(公告)日：2016-07-07

    申请号：US15072158

    申请日：2016-03-16

    申请人： SK hynix Inc.

    发明人： Seung-Hwan LEE ,  Hyun-Jeong LEE

    IPC分类号： H01L23/528 ,  H01L27/24 ,  H01L27/115 ,  H01L27/22

    CPC分类号： H01L23/528 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G11C13/0002 ,  G11C13/0009 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/11514 ,  H01L27/11597 ,  H01L27/222 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of planes vertically stacked over a substrate. Each plane includes one or more cell mats. Each cell mat includes lower lines, upper lines crossing the lower lines, and variable resistance elements positioned in intersection regions of the lower lines and the upper lines, respectively. Lower contacts are coupled to the lower lines, respectively, and, in a plan view, overlap with a boundary region between half of the upper lines and the other half number of the upper lines. Upper contacts are coupled to the upper lines, respectively, and overlap with a boundary region between a half number of the lower lines and the other half number of the lower lines. One cell mat of an upper plane is vertically stacked over a lower plane to overlap with two adjacent cell mats of the lower plane.

    摘要翻译： 电子设备包括半导体存储器。 半导体存储器包括在衬底上垂直堆叠的多个平面。 每个平面包括一个或多个细胞垫。 每个电池垫分别包括下线，与下线交叉的上线，以及位于下线和上线的交叉区域中的可变电阻元件。 下触点分别耦合到下线，并且在平面图中与上一行的一半和上一行的另一半数之间的边界区域重叠。 上触点分别耦合到上线，并且与半条下线和另一半条下线之间的边界区域重叠。 上平面的单细胞垫垂直堆叠在下平面上以与下平面的两个相邻细胞垫重叠。