公开(公告)号：US20240304730A1

公开(公告)日：2024-09-12

申请号：US18665572

申请日：2024-05-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Marcus Johannes Henricus Van Dal

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L29/06 ,  H01L29/41 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B61/00 ,  H10B63/00

CPC分类号： H01L29/78696 ,  H01L27/1207 ,  H01L29/0665 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/7853 ,  H10B61/22 ,  H10B63/30 ,  H01L29/7869

摘要： A transistor includes a first gate structure, a channel layer, and source/drain contacts. The first gate structure includes metallic nanosheets. Each of the metallic nanosheets includes a top surface, a bottom surface opposite to the top surface, and sidewalls connecting the top surface and the bottom surface. The channel layer surrounds the top surfaces, the bottom surfaces, and the sidewalls of the metallic nanosheets. The source/drain contacts are electrically connected to the channel layer. A portion of the channel layer is located between the source/drain contacts and the metallic nanosheets.

公开(公告)号：US20240105824A1

公开(公告)日：2024-03-28

申请号：US17951711

申请日：2022-09-23

申请人： Wolfspeed, Inc.

发明人： Kyle Bothe ,  Christer Hallin ,  Helder Jose DaSilva Antunes

IPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41

CPC分类号： H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/413 ,  H01L29/1608

摘要： Transistor devices are provided. In one example, the transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The transistor device includes a gate contact having a gate length of about 100 nm or less. A ratio of the gate length to a thickness of the multilayer barrier structure is in a range of about 8:1 to about 16:1.

公开(公告)号：US20230378265A1

公开(公告)日：2023-11-23

申请号：US18225177

申请日：2023-07-24

申请人： Murata Manufacturing Co., Ltd.

发明人： Hiroki SATO ,  Naruto MIYAKAWA ,  Shota USHIBA ,  Ayumi SHINAGAWA ,  Tomomi NAKANO ,  Yuka TOKUDA ,  Madoka NISHIO ,  Shinsuke TANI

IPC分类号： H01L29/06 ,  H01L29/786 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/41

CPC分类号： H01L29/0673 ,  H01L29/78696 ,  H01L29/0886 ,  H01L29/0869 ,  H01L29/1606 ,  H01L29/66045 ,  H01L29/66742 ,  H01L29/413

摘要： A field effect transistor includes a substrate, a material layer on a surface of the substrate and including a two-dimensional material or carbon nanotubes, and particles interposed between the substrate and the material layer.

公开(公告)号：US11764271B2

公开(公告)日：2023-09-19

申请号：US17684948

申请日：2022-03-02

申请人： HRL Laboratories, LLC

发明人： Joel C. Wong ,  Jeong-Sun Moon ,  Robert M. Grabar ,  Michael T. Antcliffe

IPC分类号： H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41 ,  H01L29/423 ,  H01L29/66 ,  H01L21/285 ,  H01L21/311 ,  H01L21/765 ,  H01L29/778

CPC分类号： H01L29/404 ,  H01L21/28587 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/765 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/413 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

摘要： A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck.

公开(公告)号：US20230276624A1

公开(公告)日：2023-08-31

申请号：US17682514

申请日：2022-02-28

申请人： Micron Technology, Inc.

发明人： Pankaj Sharma ,  Naveen Kaushik ,  Sidhartha Gupta

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  G11C16/04 ,  H01L29/423 ,  H01L21/28 ,  H01L29/41 ,  H01L29/51

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  G11C16/0483 ,  H01L29/42344 ,  H01L29/40117 ,  H01L29/413 ,  H01L29/517

摘要： An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures, and pillars vertically extending through the stack. The pillars comprise a tunnel dielectric material, a channel material, and an insulative material substantially surrounded by the channel material. The electronic device comprises a memory material horizontally adjacent to the conductive structures without being horizontally adjacent to the insulative structures. Related memory devices, systems, and methods of forming the electronic devices are also described.

公开(公告)号：US20230178641A1

公开(公告)日：2023-06-08

申请号：US17542322

申请日：2021-12-03

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Eunjung Cha ,  Cezar Bogdan Zota

IPC分类号： H01L29/778 ,  H01L29/43 ,  H01L29/47 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/41

CPC分类号： H01L29/778 ,  H01L29/437 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/413 ,  H01L21/28581

摘要： A transistor structure, includes a buffer layer and a quantum well channel layer on top of the buffer layer. There is a barrier layer on top of the channel layer. There is a drain contact on a channel stack. A source contact is on a channel stack. A gate structure is located between the source contact and drain contact, comprising: an active gate portion having a bottom surface in contact with a bottom surface of the source and the drain contacts. A superconducting portion of the gate structure is in contact with, and adjacent to, an upper part of the active gate portion.

公开(公告)号：US10062752B1

公开(公告)日：2018-08-28

申请号：US15793566

申请日：2017-10-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Effendi Leobandung

IPC分类号： H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L21/18 ,  H01L29/778

CPC分类号： H01L29/0669 ,  B82Y10/00 ,  H01L21/182 ,  H01L29/0676 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/413 ,  H01L29/41741 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7788

摘要： A method of forming a nanowire heterostructure, including, forming a dummy nanowire on a substrate, forming a sacrificial cover layer on the dummy nanowire, forming a spacer layer on a portion of the sacrificial cover layer, wherein a portion of the sacrificial cover layer extends above the top surface of the spacer layer, removing the portion of the sacrificial cover layer that extends above the top surface of the spacer layer, forming a gate structure on the spacer layer and a remaining portion of the sacrificial cover layer, forming an interlayer dielectric (ILD) layer on the gate structure, removing the dummy nanowire to form a nanowire trench, and forming a replacement nanowire in the nanowire trench.

公开(公告)号：US10008613B2

公开(公告)日：2018-06-26

申请号：US15096916

申请日：2016-04-12

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Shaozhuan Wang

IPC分类号： H01L27/108 ,  H01L29/94 ,  H01L29/786 ,  H01L29/06 ,  H01L29/41 ,  H01L29/423 ,  H01L27/12

CPC分类号： H01L29/78696 ,  H01L27/124 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/78642 ,  H01L29/7869

摘要： The present disclosure provides a TFT, an array substrate and a fabricating method thereof and a display device. The TFT includes a gate, an active layer, a first electrode and a second electrode, the first electrode is arranged at one side of the active layer, the second electrode is arranged at the other side of the active layer, the first electrode, the active layer and the second electrode forms a stacked structure, the gate is arranged to surround the stacked structure, and the gate and the stacked structure are insulated and separated from each other. Under fixed occupation area, the conductive channel of the TFT of the present disclosure has increased width, so drain current in saturation region is increased without impacting aperture ratio of a display panel, which further optimizes performance of the TFT and the array substrate, and improves display effect of the display device.

公开(公告)号：US09991342B2

公开(公告)日：2018-06-05

申请号：US14438497

申请日：2013-10-25

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  ALEDIA

发明人： Bérangère Hyot ,  Benoit Amstatt ,  Marie-Françoise Armand ,  Florian Dupont

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L33/04 ,  B82Y10/00 ,  B82Y40/00 ,  C30B25/00 ,  C30B25/18 ,  C30B29/16 ,  C30B29/36 ,  C30B29/40 ,  C30B29/60 ,  H01L29/40 ,  H01L29/66 ,  H01L29/41 ,  H01L33/16 ,  H01L33/12 ,  B82Y99/00 ,  H01L33/24

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  C30B25/005 ,  C30B25/183 ,  C30B29/16 ,  C30B29/36 ,  C30B29/40 ,  C30B29/406 ,  C30B29/605 ,  H01L21/02104 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02603 ,  H01L21/0262 ,  H01L29/401 ,  H01L29/413 ,  H01L29/6609 ,  H01L33/04 ,  H01L33/12 ,  H01L33/16 ,  H01L33/24 ,  Y10S977/762 ,  Y10S977/84 ,  Y10S977/932

摘要： The electronic device comprises a substrate (1), at least one semiconductor nanowire (2) and a buffer layer (3) interposed between the substrate (1) and said nanowire (2). The buffer layer (3) is at least partly formed by a transition metal nitride layer (9) from which extends the nanowire (2), said transition metal nitride being chosen from: vanadium nitride, chromium nitride, zirconium nitride, niobium nitride, molybdenum nitride, hafnium nitride or tantalum nitride.

公开(公告)号：US20180145141A1

公开(公告)日：2018-05-24

申请号：US15862742

申请日：2018-01-05

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Suyog Gupta ,  Bahman Hekmatshoartabari

IPC分类号： H01L29/423 ,  H01L21/3215 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/788 ,  H01L29/41

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/3215 ,  H01L29/413 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

摘要： A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.