公开(公告)号：US20180182879A1

公开(公告)日：2018-06-28

申请号：US15580436

申请日：2016-12-23

Applicant: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO. 55 RESEARCH INSTITUTE

Inventor： Chunjiang REN ,  Tangsheng CHEN

IPC: H01L29/778 ,  H01L29/08

CPC classification number: H01L29/7786 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02579 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/246 ,  H01L21/28575 ,  H01L21/28587 ,  H01L21/30621 ,  H01L29/06 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/454 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/66863

Abstract: A nitride high electron mobility transistor having a strain balance of an aluminum gallium nitride insertion layer is described. The transistor sequentially includes: a substrate and a GaN buffer layer located on the substrate; an AlyGa1-yN insertion layer located on the GaN buffer layer; an AlxGa1-xN barrier layer located on the AlyGa1-yN insertion layer opposite to the GaN buffer layer; a GaN cap layer located on the AlxGa1-xN barrier layer; a “┌”-shaped source electrode and drain electrode provided in recesses formed by the removal of the GaN cap layer and some thickness of the AlxGa1-xN barrier layer; and a gate electrode located between the source electrode and the drain electrode. An AlzGa1-zN insertion layer may be further included between the AlxGa1-xN barrier layer and the GaN cap layer.

公开(公告)号：US09837499B2

公开(公告)日：2017-12-05

申请号：US15326022

申请日：2014-08-13

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Sansaptak Dasgupta ,  Seung Hoon Sung ,  Sanaz Gardner ,  Marko Radosavlijevic ,  Robert Chau

IPC: H01L29/15 ,  H01L29/417 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41783 ,  H01L21/28587 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Techniques related to III-N transistors having self aligned gates, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a polarization layer between a raised source and a raised drain, a gate between the source and drain and over the polarization layer, and lateral epitaxial overgrowths over the source and drain and having and opening therebetween such that at least a portion of the gate adjacent to the polarization layer is aligned with the opening.

公开(公告)号：US20170025278A1

公开(公告)日：2017-01-26

申请号：US15285782

申请日：2016-10-05

Applicant: Raytheon Company

Inventor： Kiuchul Hwang ,  Dale M. Shaw ,  Adrian D. Williams

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/283

CPC classification number: H01L21/28114 ,  H01L21/283 ,  H01L21/28587 ,  H01L29/42316

Abstract: A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid dielectric, such as air.

Abstract translation: 具有T形电极的半导体结构。 电极具有从顶部延伸到基底表面的顶部和较窄的茎部。 固体电介质层具有与电极杆的下部的侧壁并排并邻接的侧部。 顶部的底表面通过诸如空气的非固体电介质与上表面部分间隔开。

公开(公告)号：US20160293724A1

公开(公告)日：2016-10-06

申请号：US15180851

申请日：2016-06-13

Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

Inventor： Tsutomu Komatani

IPC: H01L29/66 ,  H01L29/20 ,  H01L21/24 ,  H01L29/16 ,  H01L29/04 ,  H01L21/02 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/02359 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/246 ,  H01L21/28587 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/7787

Abstract: A method for fabricating a semiconductor device includes: forming a silicon nitride film having a refractive index equal to or larger than 2.2 on a nitride semiconductor layer; and introducing at least one of elements that are oxygen, nitrogen, fluorine, phosphorus, sulfur and selenium into the silicon nitride film, the silicon nitride film including the at least one of elements remaining on the nitride semiconductor layer. The at least one of elements is introduced by a process of exposing the silicon nitride film to plasma including the at least one of elements, a process of ion-implanting the at least one of elements into the silicon nitride film, or a process of thermally diffusing the at least one of elements into the silicon nitride film. The silicon nitride film is formed in contact with a surface of the nitride semiconductor layer.

Abstract translation: 一种制造半导体器件的方法包括：在氮化物半导体层上形成折射率等于或大于2.2的氮化硅膜; 以及将至少一种氧，氮，氟，磷，硫和硒的元素引入到氮化硅膜中，所述氮化硅膜包括留在氮化物半导体层上的至少一种元素。 所述元件中的至少一个通过将氮化硅膜暴露于包括所述至少一个元件的等离子体的工艺引入，将所述至少一个元素离子注入氮化硅膜的工艺或热 将所述至少一个元件扩散到所述氮化硅膜中。 氮化硅膜形成为与氮化物半导体层的表面接触。

公开(公告)号：US20160225888A1

公开(公告)日：2016-08-04

申请号：US15010559

申请日：2016-01-29

Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

Inventor： Ken Kikuchi

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/401 ,  H01L21/28575 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/7786 ,  H01L29/812 ,  H01L2224/11

Abstract: A process to form an electrode of a semiconductor device is disclosed. The process includes steps of: forming the first electrode on the semiconductor layer; forming the first insulating film on the first electrode, where the first insulating film provides an opening that exposes a portion of the first electrode but fully covers the semiconductor layer; fully filling the opening by the second electrode; forming the mask so as to expose the second electrode but fully cover the sides of the second electrode; forming the third electrode in a region exposing from the mask; and removing the mask.

Abstract translation: 公开了一种形成半导体器件的电极的工艺。 该方法包括以下步骤：在半导体层上形成第一电极; 在第一电极上形成第一绝缘膜，其中第一绝缘膜提供暴露第一电极的一部分但完全覆盖半导体层的开口; 通过第二电极完全填充开口; 形成所述掩模以暴露所述第二电极，但是完全覆盖所述第二电极的侧面; 在从掩模暴露的区域中形成第三电极; 并取下面罩。

公开(公告)号：US09378965B2

公开(公告)日：2016-06-28

申请号：US12653240

申请日：2009-12-10

Applicant: Michael A. Briere

Inventor： Michael A. Briere

IPC: H01L21/768 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/778

CPC classification number: H01L29/66522 ,  H01L21/28264 ,  H01L21/28587 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41725 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78

Abstract: In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors. In another embodiment, a structure for highly conductive source/drain contacts is disclosed.

Abstract translation: 在一个实施例中，公开了一种在III-氮化物半导体本体上制造III-氮化物晶体管的方法。 该方法包括：在覆盖III-氮化物半导体主体的栅极，源极和漏极区域的场电介质中蚀刻介质沟槽，之后在栅极，源极和漏极区域上形成栅极电介质。 该方法还包括在栅极介电层上形成覆盖层扩散阻挡层，然后从源极和漏极区域去除覆盖层扩散阻挡层的各个部分。 此后，从源极和漏极区域去除栅极电介质以基本上暴露源极和漏极区域。 然后，通过在源极和漏极区域中沉积接触金属来形成欧姆接触。 该方法产生特别适用于功率晶体管的高导电源极/漏极触点，例如III型氮化物晶体管，例如GaN晶体管。 在另一个实施例中，公开了一种用于高导电源极/漏极触点的结构。

公开(公告)号：US20150235856A1

公开(公告)日：2015-08-20

申请号：US14184793

申请日：2014-02-20

Applicant: Raytheon Company

Inventor： Kiuchul Hwang ,  Dale M. Shaw ,  Adrian D. Williams

IPC: H01L21/285 ,  H01L29/40 ,  H01L29/41

CPC classification number: H01L21/28587 ,  H01L21/28114 ,  H01L21/283 ,  H01L21/28537 ,  H01L29/401 ,  H01L29/41 ,  H01L29/42316

Abstract: A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid, dielectric, such as air.

Abstract translation: 具有T形电极的半导体结构。 电极具有从顶部延伸到基底表面的顶部和较窄的茎部。 固体电介质层具有与电极杆的下部的侧壁并排并邻接的侧部。 顶部的底表面通过非固体，电介质（例如空气）与上表面部分间隔开。

公开(公告)号：US09111961B2

公开(公告)日：2015-08-18

申请号：US14178701

申请日：2014-02-12

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Robert Coffie

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/3065 ,  H01L21/283 ,  H01L21/285 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L29/872 ,  H01L21/765 ,  H01L29/06 ,  H01L29/20 ,  H01L29/417 ,  H01L29/51

CPC classification number: H01L29/402 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/283 ,  H01L21/28587 ,  H01L21/30612 ,  H01L21/31105 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/518 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract translation: III-N器件描述为III-N材料层，在III-N材料层的表面上的绝缘体层，在与III-N材料层相反的绝缘体层的相对侧上的蚀刻停止层，以及 在距离绝缘体层的蚀刻停止层的相对侧上的电极限定层。 在电极限定层中形成凹部。 在凹部中形成电极。 绝缘体可以具有精确控制的厚度，特别是在电极和III-N材料层之间。

公开(公告)号：US09111786B1

公开(公告)日：2015-08-18

申请号：US14578146

申请日：2014-12-19

Applicant: Francis J. Kub ,  Travis J. Anderson ,  Michael A. Mastro ,  Charles R. Eddy, Jr. ,  Jennifer K. Hite

Inventor： Francis J. Kub ,  Travis J. Anderson ,  Michael A. Mastro ,  Charles R. Eddy, Jr. ,  Jennifer K. Hite

IPC: H01L29/778 ,  H01L27/092 ,  H01L27/095 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/04 ,  H01L29/36 ,  H01L29/78 ,  H01L29/66 ,  H01L21/335 ,  H01L21/8228 ,  H01L21/8238

CPC classification number: H01L27/095 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/26546 ,  H01L21/28575 ,  H01L21/28587 ,  H01L21/30612 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/8252 ,  H01L27/092 ,  H01L27/0921 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/1075 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/407 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/452 ,  H01L29/51 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7783 ,  H01L29/7784 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/7831

Abstract: A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.

Abstract translation: 具有N沟道和P沟道III氮化物场效应晶体管的器件包括在第一氮极氮氮III氮化物材料上的非反相P沟道III-氮化物场效应晶体管，非反相N沟道 III-氮化物场效应晶体管，外延生长，第一III-氮化物阻挡层，二维空穴气体，第二III-氮化物阻挡层和二维空穴气体。 制造互补的非反相P沟道和非反相N沟道III氮化物FET的方法，其包括生长外延层，沉积氧化物，限定开口，外延生长第一氮极III-氮化物材料，缓冲层，背部阻挡层， 通道，间隔物，阻挡层和覆盖层，载流子增强层，沉积氧化物，生长AlN成核层/极性反转层，生长中的镓极性III-氮化物，包括外延层，沉积电介质，制造P沟道III-氮化物FET ，并制造N沟道III型氮化物FET。

公开(公告)号：US20150221647A1

公开(公告)日：2015-08-06

申请号：US14578146

申请日：2014-12-19

Applicant: Francis J. Kub ,  Travis J. Anderson ,  Michael A. Mastro ,  Charles R. Eddy, JR. ,  Jennifer K. Hite

Inventor： Francis J. Kub ,  Travis J. Anderson ,  Michael A. Mastro ,  Charles R. Eddy, JR. ,  Jennifer K. Hite

IPC: H01L27/095 ,  H01L29/201 ,  H01L29/36 ,  H01L29/778 ,  H01L29/04 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L27/095 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/26546 ,  H01L21/28575 ,  H01L21/28587 ,  H01L21/30612 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/8252 ,  H01L27/092 ,  H01L27/0921 ,  H01L27/0922 ,  H01L29/045 ,  H01L29/1075 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/407 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/452 ,  H01L29/51 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7783 ,  H01L29/7784 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/7831

Abstract: A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.

Abstract translation: 具有N沟道和P沟道III氮化物场效应晶体管的器件包括在第一氮极氮氮III氮化物材料上的非反相P沟道III-氮化物场效应晶体管，非反相N沟道 III-氮化物场效应晶体管，外延生长，第一III-氮化物阻挡层，二维空穴气体，第二III-氮化物阻挡层和二维空穴气体。 制造互补的非反相P沟道和非反相N沟道III氮化物FET的方法，其包括生长外延层，沉积氧化物，限定开口，外延生长第一氮极III-氮化物材料，缓冲层，背部阻挡层， 通道，间隔物，阻挡层和覆盖层，载流子增强层，沉积氧化物，生长AlN成核层/极性反转层，生长中的镓极性III-氮化物，包括外延层，沉积电介质，制造P沟道III-氮化物FET ，并制造N沟道III型氮化物FET。