公开(公告)号：US20230131163A1

公开(公告)日：2023-04-27

申请号：US17819809

申请日：2022-08-15

Applicant: Mitsubishi Electric Corporation

Inventor： Koichi NISHI ,  Koji TANAKA ,  Shinya SONEDA ,  Shigeto HONDA ,  Naoyuki TAKEDA

IPC: H01L27/06 ,  H01L29/861 ,  H01L29/739 ,  H01L21/24 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66

Abstract: A semiconductor device includes a first electrode and a second electrode. The first electrode is connected to a collector layer and a first portion on the collector layer side of a cathode layer. The second electrode is connected to a second portion of the cathode layer excluding the first portion. A work function of the first electrode is larger than a work function of the second electrode, and one of the first electrode and the second electrode and the semiconductor substrate sandwich another of the first electrode and the second electrode in a thickness direction of the semiconductor substrate.

公开(公告)号：US11557482B2

公开(公告)日：2023-01-17

申请号：US16593392

申请日：2019-10-04

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Daniel Charles Edelstein ,  Chao-Kun Hu ,  Oscar van der Straten

IPC: H01L21/24 ,  H01L21/324 ,  H01L21/04 ,  H01L21/304 ,  H01L21/768

Abstract: An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.

公开(公告)号：US20210104406A1

公开(公告)日：2021-04-08

申请号：US16593392

申请日：2019-10-04

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Daniel Charles Edelstein ,  Chao-Kun Hu ,  Oscar Van der Straten

IPC: H01L21/24 ,  H01L21/324 ,  H01L21/768 ,  H01L21/304 ,  H01L21/04

Abstract: An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.

公开(公告)号：US20200075536A1

公开(公告)日：2020-03-05

申请号：US16228059

申请日：2018-12-20

Applicant: Ningbo Semiconductor International Corporation

Inventor： Hailong LUO ,  Clifford Ian DROWLEY

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/285 ,  H01L21/24 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

Abstract: Wafer-level packaging method and package structure are provided. In an exemplary method, first chips are bonded to the device wafer. A first encapsulation layer is formed on the device wafer, covering the first chips. The first chip includes: a chip front surface with a formed first pad, facing the device wafer; and a chip back surface opposite to the chip front surface. A first opening is formed in the first encapsulation layer to expose at least one first chip having an exposed chip back surface for receiving a loading signal. A metal layer structure is formed covering the at least one first chip, a bottom and sidewalls of the first opening, and the first encapsulation layer, followed by an alloying treatment on the chip back surface and the metal layer structure to form a back metal layer on the chip back surface.

公开(公告)号：US20190148377A1

公开(公告)日：2019-05-16

申请号：US16227215

申请日：2018-12-20

Applicant: International Business Machines Corporation

Inventor： Oleg Gluschenkov ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L27/092 ,  H01L21/24 ,  H01L29/417 ,  H01L21/02 ,  H01L21/283

Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.

公开(公告)号：US10276386B2

公开(公告)日：2019-04-30

申请号：US15638009

申请日：2017-06-29

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Ryohei Makino ,  Motoyoshi Kubouchi ,  Kiyoshi Takahashi

IPC: H01L21/24 ,  H01L21/22 ,  H01L21/288 ,  H02M7/48 ,  H05K1/00 ,  H01L25/18 ,  H01L25/11 ,  H02M7/00

Abstract: Signal relay board for power semiconductor modules enabling electrical connection between power semiconductor modules and a drive unit driving same. A first wire layer, a second wire layer, a third wire layer, and a fourth wire layer of a multiphase wire portion are assigned with a first control wire layer serving as a path to provide a control signal to a first semiconductor device of the modules, a first ground wire layer serving as a path to provide a ground potential to a low potential side terminal of the first semiconductor device of the semiconductor modules, a second control wire layer serving as a path to provide a control signal to a second semiconductor device of the modules, and a second ground wire layer serving as a path to provide a ground potential to the second semiconductor device of the modules.

公开(公告)号：US20190115347A1

公开(公告)日：2019-04-18

申请号：US15787011

申请日：2017-10-18

Applicant: International Business Machines Corporation

Inventor： Oleg Gluschenkov ,  Shogo Mochizuki ,  Hiroaki Niimi ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L27/092 ,  H01L29/417 ,  H01L21/24 ,  H01L21/283 ,  H01L21/02

Abstract: A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.

公开(公告)号：US10090198B2

公开(公告)日：2018-10-02

申请号：US14913681

申请日：2014-08-06

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Mathias Kaempf

IPC: H01L21/00 ,  H01L23/544 ,  H01L21/78 ,  B23K26/354 ,  B23K26/53 ,  B23K26/00 ,  H01L21/225 ,  H01L21/24 ,  H01L21/268 ,  H01L23/367 ,  H01L23/373 ,  H01L33/00 ,  H01L31/00 ,  B23K103/00

Abstract: Disclosed is a method for separating a substrate (1) along a separation pattern (4), in which method a substrate (1) is provided and an auxiliary layer (3) is applied to the substrate, said layer covering the substrate at least along the separation pattern. The substrate comprising the auxiliary layer is irradiated, such that the material of the auxiliary layer penetrates the substrate along the separation pattern in the form of an impurity. The substrate is broken along the separation pattern. A semiconductor chip (15) is also disclosed.

公开(公告)号：US20180061642A1

公开(公告)日：2018-03-01

申请号：US15253074

申请日：2016-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL CHIAO TUNG UNIVERSITY

Inventor： Chao-Hsin CHIEN ,  Chi-Wen LIU ,  Chung-Chun HSU ,  Wei-Chun CHI

IPC: H01L21/24 ,  H01L21/285 ,  H01L29/47 ,  H01L29/872 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy comprising components of the first metal layer, second metal layer, and the semiconductor substrate.

公开(公告)号：US09818838B2

公开(公告)日：2017-11-14

申请号：US15180851

申请日：2016-06-13

Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

Inventor： Tsutomu Komatani

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L29/778 ,  H01L29/20 ,  H01L21/24 ,  H01L29/04 ,  H01L29/16 ,  H01L21/285

CPC classification number: H01L29/66462 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/02359 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/246 ,  H01L21/28587 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/7787

Abstract: A method for fabricating a semiconductor device includes: forming a silicon nitride film having a refractive index equal to or larger than 2.2 on a nitride semiconductor layer; and introducing at least one of elements that are oxygen, nitrogen, fluorine, phosphorus, sulfur and selenium into the silicon nitride film, the silicon nitride film including the at least one of elements remaining on the nitride semiconductor layer. The at least one of elements is introduced by a process of exposing the silicon nitride film to plasma including the at least one of elements, a process of ion-implanting the at least one of elements into the silicon nitride film, or a process of thermally diffusing the at least one of elements into the silicon nitride film. The silicon nitride film is formed in contact with a surface of the nitride semiconductor layer.