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公开(公告)号：US20240079446A1
公开(公告)日：2024-03-07
申请号：US17929324
申请日：2022-09-02
发明人： Ruilong Xie , Shogo Mochizuki , Daniel Charles Edelstein , Lawrence A. Clevenger , Brent A. Anderson , Kisik Choi , Chanro Park , Christian Lavoie , Cornelius Brown Peethala , SON NGUYEN
IPC分类号： H01L29/06 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/0673 , H01L29/66439 , H01L29/66553 , H01L29/775 , H01L29/78696
摘要： Embodiments of the invention include a transistor comprising a gate region and an epitaxial region, the transistor comprising a frontside opposite a backside. A backside contact is coupled to the epitaxial region and separated from the gate region by a bottom dielectric isolation layer and a backside protective spacer
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公开(公告)号：US20230187349A1
公开(公告)日：2023-06-15
申请号：US17551675
申请日：2021-12-15
IPC分类号： H01L23/528 , H01L45/00 , H01L21/768
CPC分类号： H01L23/528 , H01L45/12 , H01L45/1608 , H01L21/76877
摘要： A semiconductor device and formation thereof. The semiconductor device including: a first bottom interconnect formed within a first dielectric layer and located within a logic area of the semiconductor device; a second bottom interconnect formed within the first dielectric layer and located within a memory area of the semiconductor device; and a memory device formed on top of the second bottom interconnect located within the memory area of the semiconductor device, wherein: a first metal material used to form the first bottom interconnect located in the logic area is different than a second metal material used to form the second bottom interconnect located in the memory area.
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公开(公告)号：US20230189671A1
公开(公告)日：2023-06-15
申请号：US17550200
申请日：2021-12-14
CPC分类号： H01L45/1253 , H01L27/11507 , H01L27/222 , H01L27/2463 , H01L43/02 , H01L43/12 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and formation thereof. The semiconductor device includes a memory device located on top of a first bottom interconnect, wherein the first bottom interconnect is embedded in a first dielectric layer. The semiconductor device further includes a second bottom interconnect embedded in the first dielectric layer, wherein the second bottom interconnect is adjacent to the first bottom interconnect. A top surface of the second bottom interconnect is recessed relative to a top surface of the first bottom interconnect.
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公开(公告)号：US20210320060A1
公开(公告)日：2021-10-14
申请号：US16842951
申请日：2020-04-08
IPC分类号： H01L23/522 , H01L21/768 , H01L43/12
摘要： A via structure and methods for forming a via structure generally includes a via opening in a dielectric layer. A conformal barrier layer is in the via opening; and a conductive metal on the barrier layer in the via opening. The conductive metal includes a recessed top surface. A conductive planarization stop layer is on the recessed top surface and extends about a shoulder portion formed in the dielectric layer, wherein the shoulder portion extends about a perimeter of the via opening. A fill material including an insulator material or a conductor material is on the conductive planarization stop layer within the recessed top surface, wherein the conductive planarization stop layer on the shoulder portion is coplanar to the insulator material or the conductor material. Also described are methods of fabricating the via structure.
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公开(公告)号：US20210183627A1
公开(公告)日：2021-06-17
申请号：US16710232
申请日：2019-12-11
IPC分类号： H01J37/32 , H01J37/305 , H01L21/683 , H01L21/67
摘要： An ion beam etching tool comprises a chuck configured to electrostatically receive a wafer; a plasma source configured to introduce an ion beam to the wafer; and a shield on the chuck and configured to shield the chuck from the ion beam. The shield comprises a material that is configured to be one of removable from the wafer or inert with regard to a semiconductor device on the wafer.
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公开(公告)号：US10892404B1
公开(公告)日：2021-01-12
申请号：US16506459
申请日：2019-07-09
摘要： A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.
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公开(公告)号：US11462583B2
公开(公告)日：2022-10-04
申请号：US16672752
申请日：2019-11-04
IPC分类号： H01L27/22 , H01L43/12 , H01L23/528 , H01L43/02
摘要： A semiconductor device structure includes a metallization stack that has one or more patterned metal layers in a logic area and a memory area. At least one memory device is disposed above the metallization stack. A first level logic metal layer is coupled to a patterned metal layer of the one or more patterned metal layers in the logic area. A first level memory metal layer is formed above the first level logic metal layer and is coupled to a top electrode of the memory device stack. A distance between the one or more patterned metal layers in the logic area and the first level logic metal layer is smaller than the distance between the one or more patterned metal layers in the memory area and the first level memory metal layer.
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公开(公告)号：US20220277964A1
公开(公告)日：2022-09-01
申请号：US17186064
申请日：2021-02-26
发明人： Mahadevaiyer Krishnan , Michael Francis Lofaro , Andrew Giannetta , Douglas Bishop , Eugene J. O'Sullivan , Daniel Charles Edelstein
IPC分类号： H01L21/321 , H01L21/768 , C09G1/02
摘要： A method for planarizing a metal conductor layer embedded in a dielectric layer is provided. The method includes removing a portion of an overburden of the metal conductor layer that is formed over the dielectric layer with a first CMP slurry. The method also includes removing a remaining portion of the overburden of the metal conductor layer with a second CMP slurry to expose upper portions of the dielectric layer.
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公开(公告)号：US20210296118A1
公开(公告)日：2021-09-23
申请号：US16824559
申请日：2020-03-19
发明人： Devika Sil , Ashim Dutta , Yann Mignot , John Christopher Arnold , Daniel Charles Edelstein , Kedari Matam , Cornelius Brown Peethala
IPC分类号： H01L21/02 , H01L21/3065
摘要： A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer; and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.
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公开(公告)号：US11031542B2
公开(公告)日：2021-06-08
申请号：US16401206
申请日：2019-05-02
摘要： Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.
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