公开(公告)号：US10199217B2

公开(公告)日：2019-02-05

申请号：US15288120

申请日：2016-10-07

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Umesh Mishra ,  Rakesh K. Lal

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/861 ,  H01L23/29 ,  H01L23/31 ,  H01L29/423 ,  H01L23/00

Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

公开(公告)号：US09111961B2

公开(公告)日：2015-08-18

申请号：US14178701

申请日：2014-02-12

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Robert Coffie

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/3065 ,  H01L21/283 ,  H01L21/285 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L29/872 ,  H01L21/765 ,  H01L29/06 ,  H01L29/20 ,  H01L29/417 ,  H01L29/51

CPC classification number: H01L29/402 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/283 ,  H01L21/28587 ,  H01L21/30612 ,  H01L21/31105 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/518 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract translation: III-N器件描述为III-N材料层，在III-N材料层的表面上的绝缘体层，在与III-N材料层相反的绝缘体层的相对侧上的蚀刻停止层，以及 在距离绝缘体层的蚀刻停止层的相对侧上的电极限定层。 在电极限定层中形成凹部。 在凹部中形成电极。 绝缘体可以具有精确控制的厚度，特别是在电极和III-N材料层之间。

公开(公告)号：US20130210220A1

公开(公告)日：2013-08-15

申请号：US13756284

申请日：2013-01-31

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Umesh Mishra ,  Rakesh K. Lal

IPC: H01L21/02

CPC classification number: H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/06 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/861 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/06183 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/1032 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2224/03 ,  H01L2924/00

Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

Abstract translation: 描述了包括III族氮化物层，钝化层和导电触点的堆叠的III族氮化物器件。 该堆叠包括具有2DEG通道的通道层，阻挡层和间隔层。 一个钝化层直接接触与沟道层相对的一侧的间隔层的表面，并且是一个电绝缘体。 III族氮化物层和第一钝化层的堆叠形成具有靠近第一钝化层的反面和靠近阻挡层的正面的结构。 另一个钝化层位于结构的正面。 在形成过程中形成缓冲层的缺陷成核和应力管理层可以被部分或完全去除。

公开(公告)号：US09496137B2

公开(公告)日：2016-11-15

申请号：US13756284

申请日：2013-01-31

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Umesh Mishra ,  Rakesh K. Lal

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/423 ,  H01L23/00

CPC classification number: H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/06 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/861 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/06183 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/1032 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2224/03 ,  H01L2924/00

Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

Abstract translation: 描述了包括III族氮化物层，钝化层和导电触点的堆叠的III族氮化物器件。 该堆叠包括具有2DEG通道的通道层，阻挡层和间隔层。 一个钝化层直接接触与沟道层相对的一侧的间隔层的表面，并且是一个电绝缘体。 III族氮化物层和第一钝化层的堆叠形成具有靠近第一钝化层的反面和靠近阻挡层的正面的结构。 另一个钝化层位于结构的正面。 在形成过程中形成缓冲层的缺陷成核和应力管理层可以被部分或完全去除。

公开(公告)号：US20160293747A1

公开(公告)日：2016-10-06

申请号：US15181805

申请日：2016-06-14

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Robert Coffie

IPC: H01L29/778 ,  H01L29/51 ,  H01L29/417 ,  H01L29/423 ,  H01L29/20 ,  H01L29/40

CPC classification number: H01L29/402 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/283 ,  H01L21/28587 ,  H01L21/30612 ,  H01L21/31105 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/518 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

公开(公告)号：US20170025267A1

公开(公告)日：2017-01-26

申请号：US15288120

申请日：2016-10-07

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Umesh Mishra ,  Rakesh K. Lal

IPC: H01L21/02 ,  H01L29/861 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/06 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/861 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/06183 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/1032 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2224/03 ,  H01L2924/00

Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

Abstract translation: 描述了包括III族氮化物层，钝化层和导电触点的堆叠的III族氮化物器件。 该堆叠包括具有2DEG通道的通道层，阻挡层和间隔层。 一个钝化层直接接触与沟道层相对的一侧的间隔层的表面，并且是一个电绝缘体。 III族氮化物层和第一钝化层的堆叠形成具有靠近第一钝化层的反面和靠近阻挡层的正面的结构。 另一个钝化层位于结构的正面。 在形成过程中形成缓冲层的缺陷成核和应力管理层可以被部分或完全去除。

公开(公告)号：US09041065B2

公开(公告)日：2015-05-26

申请号：US13973890

申请日：2013-08-22

Applicant: Transphorm Inc.

Inventor： Yifeng Wu ,  Umesh Mishra ,  Primit Parikh ,  Rongming Chu ,  Ilan Ben-Yaacov ,  Likun Shen

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/872 ,  H01L27/06 ,  H01L29/778 ,  H01L29/423

CPC classification number: H01L29/0615 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.

Abstract translation: 平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。 金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。 金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

公开(公告)号：US09831315B2

公开(公告)日：2017-11-28

申请号：US15181805

申请日：2016-06-14

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Robert Coffie

IPC: H01L29/40 ,  H01L21/283 ,  H01L21/02 ,  H01L29/78 ,  H01L21/306 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  H01L29/51 ,  H01L21/765 ,  H01L29/417 ,  H01L21/285 ,  H01L29/20 ,  H01L29/872

CPC classification number: H01L29/402 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/283 ,  H01L21/28587 ,  H01L21/30612 ,  H01L21/31105 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/518 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

公开(公告)号：US09012288B2

公开(公告)日：2015-04-21

申请号：US14178701

申请日：2014-02-12

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Robert Coffie

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/3065 ,  H01L21/283 ,  H01L21/285 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L29/872 ,  H01L21/765 ,  H01L29/06 ,  H01L29/20 ,  H01L29/417 ,  H01L29/51

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

公开(公告)号：US08692294B2

公开(公告)日：2014-04-08

申请号：US13748907

申请日：2013-01-24

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Robert Coffie

IPC: H01L29/08 ,  H01L29/47 ,  H01L29/778 ,  H01L21/765 ,  H01L21/335

CPC classification number: H01L29/402 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/283 ,  H01L21/28587 ,  H01L21/30612 ,  H01L21/31105 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/518 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract translation: III-N器件描述为III-N材料层，在III-N材料层的表面上的绝缘体层，在与III-N材料层相反的绝缘体层的相对侧上的蚀刻停止层，以及 在距离绝缘体层的蚀刻停止层的相对侧上的电极限定层。 在电极限定层中形成凹部。 在凹部中形成电极。 绝缘体可以具有精确控制的厚度，特别是在电极和III-N材料层之间。