公开(公告)号：US10043896B2

公开(公告)日：2018-08-07

申请号：US15836157

申请日：2017-12-08

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Rakesh K. Lal ,  Stacia Keller ,  Srabanti Chowdhury

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/15 ,  H01L29/04 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/51

Abstract: A transistor includes a III-N layer structure including a III-N channel layer between a III-N barrier layer and a III-N depleting layer, where the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer; a source and a drain, each of which being directly connected to the III-N channel layer; a gate between the source and the drain, the gate being over the III-N layer structure, where the III-N depleting layer includes a first portion that is disposed in a device access region between the gate and the drain; and where the source electrically contacts the first portion of the III-N depleting layer, and the drain is electrically isolated from the first portion of the III-N depleting layer.

公开(公告)号：US09634100B2

公开(公告)日：2017-04-25

申请号：US14934565

申请日：2015-11-06

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Srabanti Chowdhury ,  Ilan Ben-Yaacov

IPC: H01L31/0328 ,  H01L29/40 ,  H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/207 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/402 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/7786 ,  H01L29/78

Abstract: Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.

公开(公告)号：US20170025267A1

公开(公告)日：2017-01-26

申请号：US15288120

申请日：2016-10-07

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Umesh Mishra ,  Rakesh K. Lal

IPC: H01L21/02 ,  H01L29/861 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/06 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/861 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/06183 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/1032 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2224/03 ,  H01L2924/00

Abstract: Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

Abstract translation: 描述了包括III族氮化物层，钝化层和导电触点的堆叠的III族氮化物器件。 该堆叠包括具有2DEG通道的通道层，阻挡层和间隔层。 一个钝化层直接接触与沟道层相对的一侧的间隔层的表面，并且是一个电绝缘体。 III族氮化物层和第一钝化层的堆叠形成具有靠近第一钝化层的反面和靠近阻挡层的正面的结构。 另一个钝化层位于结构的正面。 在形成过程中形成缓冲层的缺陷成核和应力管理层可以被部分或完全去除。

公开(公告)号：US20160359030A1

公开(公告)日：2016-12-08

申请号：US15242266

申请日：2016-08-19

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Robert Coffie ,  Likun Shen ,  Ilan Ben-Yaacov ,  Primit Parikh

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/207 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7784 ,  H01L21/0217 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7788

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

公开(公告)号：US09443938B2

公开(公告)日：2016-09-13

申请号：US14327371

申请日：2014-07-09

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Rakesh K. Lal ,  Stacia Keller ,  Srabanti Chowdhury

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/04 ,  H01L29/51

CPC classification number: H01L29/7783 ,  H01L29/045 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/51 ,  H01L29/66462

Abstract: A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.

Abstract translation: 晶体管包括III-N层结构，其包含在III-N势垒层和p型III-N层之间的III-N沟道层。 晶体管还包括源极和漏极之间的源极，漏极和栅极，栅极在III-N层结构之上。 p型III-N层包括至少部分地在栅极和漏极之间的器件访问区域中的第一部分，并且p型III-N层的第一部分电连接到源极和电 从排水沟隔离。 当晶体管偏置为截止状态时，p型层可能导致器件访问区域中的沟道电荷随漏极电压增加而消耗，从而导致更高的击穿电压。

公开(公告)号：US09293561B2

公开(公告)日：2016-03-22

申请号：US14262649

申请日：2014-04-25

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Lee McCarthy ,  Nicholas Fichtenbaum

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/02 ,  H01L29/207

CPC classification number: H01L29/66462 ,  H01L21/0254 ,  H01L21/02581 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/7787

Abstract: A III-N device is described has a buffer layer, a first III-N material layer on the buffer layer, a second III-N material layer on the first III-N material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a 2DEG channel in the first III-N material layer. A sheet or a distribution of negative charge at an interface of the channel layer and the dispersion blocking layer confines electrons away from the buffer layer.

Abstract translation: 描述了III-N器件具有缓冲层，缓冲层上的第一III-N材料层，与缓冲层相反侧的第一III-N材料层上的第二III-N材料层和分散体 缓冲层和通道层之间的阻挡层。 第一III-N材料层是沟道层，并且第一III-N材料层和第二III-N材料层之间的组成差异在第一III-N材料层中诱导2DEG沟道。 在沟道层和分散阻挡层的界面处的负电荷的片材或分布限制电子远离缓冲层。

公开(公告)号：US09293458B2

公开(公告)日：2016-03-22

申请号：US14058089

申请日：2013-10-18

Applicant: Transphorm Inc.

Inventor： Primit Parikh ,  James Honea ,  Carl C. Blake, Jr. ,  Robert Coffie ,  Yifeng Wu ,  Umesh Mishra

IPC: H03K17/687 ,  H01L27/088 ,  H01L21/8258 ,  H01L27/06 ,  H03K17/567 ,  H01L23/495 ,  H01L25/16 ,  H01L23/64 ,  H01L25/18

CPC classification number: H01L27/0883 ,  H01L21/8258 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/642 ,  H01L23/647 ,  H01L25/165 ,  H01L25/18 ,  H01L27/0605 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.

Abstract translation: 电子部件包括高压耗尽型晶体管和低压增强型晶体管，两者都封装在单个封装中。 高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的漏极电连接到漏极引线 单个封装，低电压增强型晶体管的栅电极电连接到单个封装的栅极引线，高电压耗尽型晶体管的栅极电连接到单个封装的附加引线 并且低电压增强型晶体管的源电极电连接到单个封装的导电结构部分。

公开(公告)号：US09224671B2

公开(公告)日：2015-12-29

申请号：US14522154

申请日：2014-10-23

Applicant: Transphorm Inc.

Inventor： Primit Parikh ,  Yuvaraj Dora ,  Yifeng Wu ,  Umesh Mishra ,  Nicholas Fichtenbaum ,  Rakesh K. Lal

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/12 ,  H01L21/18 ,  H01L23/34 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/778 ,  H01L21/02 ,  H01L21/48 ,  H01L21/762 ,  H01L29/30 ,  H01L23/373

CPC classification number: H01L23/34 ,  H01L21/02118 ,  H01L21/0254 ,  H01L21/486 ,  H01L21/76254 ,  H01L23/3732 ,  H01L23/3738 ,  H01L29/0657 ,  H01L29/1075 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/30 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

Abstract translation: III-N器件用III-N层，其上的电极，与III-N层和电极相邻的钝化层，与钝化层和电极相邻的厚绝缘层，能够转移大量的高导热载体 远离III-N器件的热量，以及厚绝缘层和载体之间的结合层。 接合层将厚绝缘层附着到载体上。 厚的绝缘层可以具有精确控制的厚度并且是导热的。

公开(公告)号：US09041065B2

公开(公告)日：2015-05-26

申请号：US13973890

申请日：2013-08-22

Applicant: Transphorm Inc.

Inventor： Yifeng Wu ,  Umesh Mishra ,  Primit Parikh ,  Rongming Chu ,  Ilan Ben-Yaacov ,  Likun Shen

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/872 ,  H01L27/06 ,  H01L29/778 ,  H01L29/423

CPC classification number: H01L29/0615 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/872

Abstract: Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.

Abstract translation: 平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。 金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。 金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

公开(公告)号：US20140299940A1

公开(公告)日：2014-10-09

申请号：US14311600

申请日：2014-06-23

Applicant: Transphorm Inc.

Inventor： Yifeng Wu ,  Umesh Mishra ,  Srabanti Chowdhury

IPC: H01L27/088 ,  H01L29/20

CPC classification number: H01L27/0883 ,  H01L27/0605 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/778 ,  H03K17/687

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, and a gate electrode of the high-voltage depletion-mode transistor is electrically coupled to the source electrode of the low-voltage enhancement-mode transistor. The on-resistance of the enhancement-mode transistor is less than the on-resistance of the depletion-mode transistor, and the maximum current level of the enhancement-mode transistor is smaller than the maximum current level of the depletion-mode transistor.