公开(公告)号：US20160359030A1

公开(公告)日：2016-12-08

申请号：US15242266

申请日：2016-08-19

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Robert Coffie ,  Likun Shen ,  Ilan Ben-Yaacov ,  Primit Parikh

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/207 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7784 ,  H01L21/0217 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7788

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

公开(公告)号：US09293458B2

公开(公告)日：2016-03-22

申请号：US14058089

申请日：2013-10-18

Applicant: Transphorm Inc.

Inventor： Primit Parikh ,  James Honea ,  Carl C. Blake, Jr. ,  Robert Coffie ,  Yifeng Wu ,  Umesh Mishra

IPC: H03K17/687 ,  H01L27/088 ,  H01L21/8258 ,  H01L27/06 ,  H03K17/567 ,  H01L23/495 ,  H01L25/16 ,  H01L23/64 ,  H01L25/18

CPC classification number: H01L27/0883 ,  H01L21/8258 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/642 ,  H01L23/647 ,  H01L25/165 ,  H01L25/18 ,  H01L27/0605 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.

Abstract translation: 电子部件包括高压耗尽型晶体管和低压增强型晶体管，两者都封装在单个封装中。 高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的漏极电连接到漏极引线 单个封装，低电压增强型晶体管的栅电极电连接到单个封装的栅极引线，高电压耗尽型晶体管的栅极电连接到单个封装的附加引线 并且低电压增强型晶体管的源电极电连接到单个封装的导电结构部分。

公开(公告)号：US09171836B2

公开(公告)日：2015-10-27

申请号：US14478504

申请日：2014-09-05

Applicant: Transphorm Inc.

Inventor： Rakesh K. Lal ,  Robert Coffie ,  Yifeng Wu ,  Primit Parikh ,  Yuvaraj Dora ,  Umesh Mishra ,  Srabanti Chowdhury ,  Nicholas Fichtenbaum

IPC: H03K17/687 ,  H01L27/02 ,  H01L25/00 ,  H01L21/8236 ,  H01L27/06 ,  H01L49/02 ,  H01L29/778 ,  H03K17/10 ,  H01L29/423 ,  H01L29/872 ,  H01L29/20

CPC classification number: H01L27/0288 ,  H01L21/8236 ,  H01L25/00 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7786 ,  H01L29/872 ,  H01L2924/0002 ,  H03K17/102 ,  H03K2017/6875 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

Abstract translation: 电子部件包括耗尽型晶体管，增强型晶体管和电阻。 耗尽型晶体管具有比增强型晶体管更高的击穿电压。 电阻器的第一端子电连接到增强型晶体管的源极，并且电阻器的第二端子和耗尽型晶体管的源极电连接到增强型晶体管的漏极。 耗尽型晶体管的栅极可以电连接到增强型晶体管的源极。

公开(公告)号：US09111961B2

公开(公告)日：2015-08-18

申请号：US14178701

申请日：2014-02-12

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Robert Coffie

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/3065 ,  H01L21/283 ,  H01L21/285 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L29/872 ,  H01L21/765 ,  H01L29/06 ,  H01L29/20 ,  H01L29/417 ,  H01L29/51

CPC classification number: H01L29/402 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/283 ,  H01L21/28587 ,  H01L21/30612 ,  H01L21/31105 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/518 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract translation: III-N器件描述为III-N材料层，在III-N材料层的表面上的绝缘体层，在与III-N材料层相反的绝缘体层的相对侧上的蚀刻停止层，以及 在距离绝缘体层的蚀刻停止层的相对侧上的电极限定层。 在电极限定层中形成凹部。 在凹部中形成电极。 绝缘体可以具有精确控制的厚度，特别是在电极和III-N材料层之间。

公开(公告)号：US20140361309A1

公开(公告)日：2014-12-11

申请号：US14464639

申请日：2014-08-20

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Robert Coffie ,  Likun Shen ,  Ilan Ben-Yaacov ,  Primit Parikh

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7784 ,  H01L21/0217 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7788

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

Abstract translation: 一种III-N半导体器件，其包括衬底和包括部分在栅极区域下方的区域的氮化物沟道层，以及在栅极下方的部分的相对侧上的两个沟道存取区域。 通道接入区域可以在与栅极下方的区域不同的层中。 该器件包括与沟道层相邻的AlXN层，其中X是镓，铟或它们的组合，以及在与沟道接入区相邻的区域中与AlXN层相邻的优选n掺杂GaN层。 选择AlXN层中的Al的浓度，n掺杂GaN层中的AlXN层厚度和n掺杂浓度，以在沟道接入区域中引起2DEG电荷，而不在栅极下方引起任何实质的2DEG电荷，使得 在没有施加到栅极的开关电压的情况下，通道不导通。

公开(公告)号：US20140042495A1

公开(公告)日：2014-02-13

申请号：US14058089

申请日：2013-10-18

Applicant: Transphorm Inc.

Inventor： Primit Parikh ,  James Honea ,  Carl C. Blake, Jr. ,  Robert Coffie ,  Yifeng Wu ,  Umesh Mishra

IPC: H01L27/088

CPC classification number: H01L27/0883 ,  H01L21/8258 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/642 ,  H01L23/647 ,  H01L25/165 ,  H01L25/18 ,  H01L27/0605 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03K17/567 ,  H01L2924/00

Abstract: An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.

Abstract translation: 电子部件包括高压耗尽型晶体管和低压增强型晶体管，两者都封装在单个封装中。 高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的漏极电连接到漏极引线 单个封装，低电压增强型晶体管的栅电极电连接到单个封装的栅极引线，高电压耗尽型晶体管的栅极电连接到单个封装的附加引线 并且低电压增强型晶体管的源电极电连接到单个封装的导电结构部分。

公开(公告)号：US20130316502A1

公开(公告)日：2013-11-28

申请号：US13954772

申请日：2013-07-30

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Robert Coffie ,  Likun Shen ,  Ilan Ben-Yaacov ,  Primit Parikh

IPC: H01L29/66

CPC classification number: H01L29/7784 ,  H01L21/0217 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7788

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

公开(公告)号：US09941399B2

公开(公告)日：2018-04-10

申请号：US15242266

申请日：2016-08-19

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Robert Coffie ,  Likun Shen ,  Ilan Ben-Yaacov ,  Primit Parikh

IPC: H03H11/46 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/36 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L29/205 ,  H01L29/207 ,  H01L29/51

CPC classification number: H01L29/7784 ,  H01L21/0217 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7788

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

公开(公告)号：US09437708B2

公开(公告)日：2016-09-06

申请号：US14945341

申请日：2015-11-18

Applicant: Transphorm Inc.

Inventor： Umesh Mishra ,  Robert Coffie ,  Likun Shen ,  Ilan Ben-Yaacov ,  Primit Parikh

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/36 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L29/205 ,  H01L29/207 ,  H01L29/51

CPC classification number: H01L29/7784 ,  H01L21/0217 ,  H01L21/0254 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/365 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7788

Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

公开(公告)号：US09373699B2

公开(公告)日：2016-06-21

申请号：US14660080

申请日：2015-03-17

Applicant: Transphorm Inc.

Inventor： Rongming Chu ,  Robert Coffie

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/3065 ,  H01L21/283 ,  H01L29/12 ,  H01L21/18 ,  H01L21/285 ,  H01L29/20 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L29/872 ,  H01L21/765 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/78 ,  H01L29/417 ,  H01L29/51

CPC classification number: H01L29/402 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/283 ,  H01L21/28587 ,  H01L21/30612 ,  H01L21/31105 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/518 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/872

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.