公开(公告)号：US20180315843A1

公开(公告)日：2018-11-01

申请号：US16029505

申请日：2018-07-06

申请人： Transphorm Inc.

发明人： Rakesh K. Lal

IPC分类号： H01L29/778 ,  H01L29/423 ,  H01L21/8252 ,  H01L29/78 ,  H01L29/66 ,  H01L23/535 ,  H01L29/417 ,  H01L27/06 ,  H01L27/085 ,  H01L27/088 ,  H01L29/20 ,  H01L29/40 ,  H01L23/29 ,  H01L21/02 ,  H01L23/31 ,  H01L23/00 ,  H01L29/51

CPC分类号： H01L29/7787 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/535 ,  H01L24/48 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/085 ,  H01L27/0883 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/78 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2924/00014 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099

摘要： A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

公开(公告)号：US10043896B2

公开(公告)日：2018-08-07

申请号：US15836157

申请日：2017-12-08

申请人： Transphorm Inc.

发明人： Umesh Mishra ,  Rakesh K. Lal ,  Stacia Keller ,  Srabanti Chowdhury

IPC分类号： H01L29/06 ,  H01L29/778 ,  H01L29/15 ,  H01L29/04 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/51

摘要： A transistor includes a III-N layer structure including a III-N channel layer between a III-N barrier layer and a III-N depleting layer, where the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer; a source and a drain, each of which being directly connected to the III-N channel layer; a gate between the source and the drain, the gate being over the III-N layer structure, where the III-N depleting layer includes a first portion that is disposed in a device access region between the gate and the drain; and where the source electrically contacts the first portion of the III-N depleting layer, and the drain is electrically isolated from the first portion of the III-N depleting layer.

公开(公告)号：US20170025267A1

公开(公告)日：2017-01-26

申请号：US15288120

申请日：2016-10-07

申请人： Transphorm Inc.

发明人： Rongming Chu ,  Umesh Mishra ,  Rakesh K. Lal

IPC分类号： H01L21/02 ,  H01L29/861 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66

CPC分类号： H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/06 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/861 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/06183 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/1032 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2224/03 ,  H01L2924/00

摘要： Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

摘要翻译： 描述了包括III族氮化物层，钝化层和导电触点的堆叠的III族氮化物器件。 该堆叠包括具有2DEG通道的通道层，阻挡层和间隔层。 一个钝化层直接接触与沟道层相对的一侧的间隔层的表面，并且是一个电绝缘体。 III族氮化物层和第一钝化层的堆叠形成具有靠近第一钝化层的反面和靠近阻挡层的正面的结构。 另一个钝化层位于结构的正面。 在形成过程中形成缓冲层的缺陷成核和应力管理层可以被部分或完全去除。

公开(公告)号：US09443938B2

公开(公告)日：2016-09-13

申请号：US14327371

申请日：2014-07-09

申请人： Transphorm Inc.

发明人： Umesh Mishra ,  Rakesh K. Lal ,  Stacia Keller ,  Srabanti Chowdhury

IPC分类号： H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/04 ,  H01L29/51

CPC分类号： H01L29/7783 ,  H01L29/045 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/51 ,  H01L29/66462

摘要： A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.

摘要翻译： 晶体管包括III-N层结构，其包含在III-N势垒层和p型III-N层之间的III-N沟道层。 晶体管还包括源极和漏极之间的源极，漏极和栅极，栅极在III-N层结构之上。 p型III-N层包括至少部分地在栅极和漏极之间的器件访问区域中的第一部分，并且p型III-N层的第一部分电连接到源极和电 从排水沟隔离。 当晶体管偏置为截止状态时，p型层可能导致器件访问区域中的沟道电荷随漏极电压增加而消耗，从而导致更高的击穿电压。

公开(公告)号：US09224671B2

公开(公告)日：2015-12-29

申请号：US14522154

申请日：2014-10-23

申请人： Transphorm Inc.

发明人： Primit Parikh ,  Yuvaraj Dora ,  Yifeng Wu ,  Umesh Mishra ,  Nicholas Fichtenbaum ,  Rakesh K. Lal

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/12 ,  H01L21/18 ,  H01L23/34 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/778 ,  H01L21/02 ,  H01L21/48 ,  H01L21/762 ,  H01L29/30 ,  H01L23/373

CPC分类号： H01L23/34 ,  H01L21/02118 ,  H01L21/0254 ,  H01L21/486 ,  H01L21/76254 ,  H01L23/3732 ,  H01L23/3738 ,  H01L29/0657 ,  H01L29/1075 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/30 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

摘要： A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.

摘要翻译： III-N器件用III-N层，其上的电极，与III-N层和电极相邻的钝化层，与钝化层和电极相邻的厚绝缘层，能够转移大量的高导热载体 远离III-N器件的热量，以及厚绝缘层和载体之间的结合层。 接合层将厚绝缘层附着到载体上。 厚的绝缘层可以具有精确控制的厚度并且是导热的。

公开(公告)号：US09087718B2

公开(公告)日：2015-07-21

申请号：US13799989

申请日：2013-03-13

申请人： Transphorm Inc.

发明人： Rakesh K. Lal

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L29/423

CPC分类号： H01L29/7787 ,  H01L21/0217 ,  H01L21/0254 ,  H01L21/8252 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/535 ,  H01L24/48 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/085 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/78 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2924/00014 ,  H01L2924/10323 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/10346 ,  H01L2924/13055 ,  H01L2924/13064 ,  H01L2924/00 ,  H01L2224/45099

摘要： A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

摘要翻译： III-N增强型晶体管包括III-N结构，其包括导电沟道，源极和漏极接触以及源极和漏极接触之间的栅电极。 绝缘体层在III-N结构之上，在晶体管的栅极区中通过绝缘体层形成凹槽，栅电极至少部分地在凹槽中。 晶体管还包括具有在栅电极和漏极接触之间的部分的场板，场板电连接到源触点。 栅极电极包括在凹部外部并朝向漏极接触部延伸的延伸部分。 导电沟道和栅电极的延伸部分之间的间隔大于导电通道与栅电极和漏极接触之间的场板部分之间的间隔。

公开(公告)号：US20200119179A1

公开(公告)日：2020-04-16

申请号：US16598510

申请日：2019-10-10

申请人： Transphorm Inc.

发明人： Umesh Mishra ,  Davide Bisi ,  Geetak Gupta ,  Carl Joseph Neufeld ,  Brian L. Swenson ,  Rakesh K. Lal

IPC分类号： H01L29/778 ,  H01L29/205 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

摘要： A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.

公开(公告)号：US20190198615A1

公开(公告)日：2019-06-27

申请号：US16287211

申请日：2019-02-27

申请人： Transphorm Inc.

发明人： Umesh Mishra ,  Rakesh K. Lal ,  Geetak Gupta ,  Carl Joseph Neufeld ,  David Rhodes

IPC分类号： H01L29/06 ,  H01L29/205 ,  H01L29/20 ,  H01L29/778 ,  H01L29/40 ,  H01L29/872 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

CPC分类号： H01L29/0688 ,  H01L23/49562 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7785 ,  H01L29/7786 ,  H01L29/872

摘要： A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.

公开(公告)号：US09935190B2

公开(公告)日：2018-04-03

申请号：US15065597

申请日：2016-03-09

申请人： Transphorm Inc.

发明人： Mo Wu ,  Rakesh K. Lal ,  Ilan Ben-Yaacov ,  Umesh Mishra ,  Carl Joseph Neufeld

IPC分类号： H01L29/00 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L21/28 ,  H01L29/205 ,  H01L29/51 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L29/423 ,  H01L29/10 ,  H01L21/02

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/28264 ,  H01L21/30617 ,  H01L21/30621 ,  H01L21/3081 ,  H01L21/31144 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

摘要： A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.

公开(公告)号：US09496137B2

公开(公告)日：2016-11-15

申请号：US13756284

申请日：2013-01-31

申请人： Transphorm Inc.

发明人： Rongming Chu ,  Umesh Mishra ,  Rakesh K. Lal

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/423 ,  H01L23/00

CPC分类号： H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/06 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/42316 ,  H01L29/6609 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/861 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/06183 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/1032 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2224/03 ,  H01L2924/00

摘要： Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

摘要翻译： 描述了包括III族氮化物层，钝化层和导电触点的堆叠的III族氮化物器件。 该堆叠包括具有2DEG通道的通道层，阻挡层和间隔层。 一个钝化层直接接触与沟道层相对的一侧的间隔层的表面，并且是一个电绝缘体。 III族氮化物层和第一钝化层的堆叠形成具有靠近第一钝化层的反面和靠近阻挡层的正面的结构。 另一个钝化层位于结构的正面。 在形成过程中形成缓冲层的缺陷成核和应力管理层可以被部分或完全去除。