公开(公告)号：US11923245B2

公开(公告)日：2024-03-05

申请号：US17795900

申请日：2021-02-03

申请人： Bowling Green State University

发明人： Farida Selim

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L29/778

CPC分类号： H01L21/76886 ,  H01L21/02172 ,  H01L21/02241 ,  H01L21/02345 ,  H01L29/7783

摘要： Methods for inducing reversible or permanent conductivity in wide band gap metal oxides such as Ga2O3, using light without doping, as well as related compositions and devices, are described.

公开(公告)号：US11757028B2

公开(公告)日：2023-09-12

申请号：US17559148

申请日：2021-12-22

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

发明人： Yosuke Kajiwara ,  Daimotsu Kato ,  Masahiko Kuraguchi

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/7787 ,  H01L21/02458 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66462 ,  H01L21/02241 ,  H01L21/02326

摘要： According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.

公开(公告)号：US20230144369A1

公开(公告)日：2023-05-11

申请号：US17671555

申请日：2022-02-14

申请人： INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.

发明人： Yi-Lun CHOU ,  Shuang GAO ,  Chuangang LI

IPC分类号： H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L21/306 ,  H01L21/76 ,  H01L29/66

CPC分类号： H01L29/7786 ,  H01L29/0642 ,  H01L29/2003 ,  H01L29/205 ,  H01L21/0254 ,  H01L21/02241 ,  H01L21/30612 ,  H01L21/7605 ,  H01L29/66462

摘要： A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a lattice layer, a third nitride-based semiconductor layer, a first source electrode and a second electrode, and a gate electrode. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer. The lattice layer is disposed between the first and second nitride-based semiconductor layers and doped to the first conductivity type. The lattice layer comprises a plurality of first III-V layers and a plurality of second III-V layers alternatively stacked. Each of the first III-V layers has a high resistivity region and a current aperture enclosed by the high resistivity region. The high resistivity region comprises more metal oxides than the current aperture. Interfaces formed between the high resistivity regions and the current apertures among the first III-V layers align with each other. The gate electrode aligns with the current aperture.

公开(公告)号：US20180197979A1

公开(公告)日：2018-07-12

申请号：US15911920

申请日：2018-03-05

申请人： FUJITSU LIMITED

发明人： Shirou OZAKI ,  Kozo Makiyama ,  NAOYA OKAMOTO

IPC分类号： H01L29/778 ,  H01L29/51 ,  H01L29/205 ,  H01L29/20 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L29/7787 ,  H01L21/02172 ,  H01L21/02178 ,  H01L21/02241 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/475 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7786

摘要： A semiconductor device includes a semiconductor stacked structure in which a semiconductor layer including an electron supply layer and an electron transit layer is stacked, and a gate electrode contacting with the semiconductor layer included in the semiconductor stacked structure or an insulating layer. The portion of the gate electrode contacting with the semiconductor layer or the insulating layer is an oxide of a metal configuring the portion of the gate electrode contacting with the semiconductor layer or the insulating layer.

公开(公告)号：US09984873B2

公开(公告)日：2018-05-29

申请号：US15288207

申请日：2016-10-07

申请人： International Business Machines Corporation

发明人： Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC分类号： H01L29/205 ,  H01L21/02 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L21/02546 ,  H01L21/02178 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/0251 ,  H01L29/0692 ,  H01L29/1054 ,  H01L29/205

摘要： A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.

公开(公告)号：US20180090595A1

公开(公告)日：2018-03-29

申请号：US15652951

申请日：2017-07-18

申请人： FUJITSU LIMITED

发明人： Shirou OZAKI

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/417

CPC分类号： H01L29/66522 ,  H01L21/02241 ,  H01L21/28264 ,  H01L21/30612 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： A semiconductor device includes a first semiconductor layer formed of a compound semiconductor, provided over a substrate; a second semiconductor layer formed of a compound semiconductor including In and Al, provided over the first semiconductor layer; source and drain electrodes provided on the second semiconductor layer; and a gate electrode provided between the source and drain electrodes, on the second semiconductor layer. The compound semiconductor in the second semiconductor layer has a first In composition ratio in a region on a side facing the substrate and a second In composition ratio in a region on an opposite side, the second In composition ratio being lower than the first In composition ratio, and the source and drain electrodes are provided in contact with the region having the first In composition ratio, and the gate electrode is provided on the region having the second In composition ratio.

公开(公告)号：US20180061954A1

公开(公告)日：2018-03-01

申请号：US15687302

申请日：2017-08-25

申请人： OSAKA UNIVERSITY

发明人： Heiji WATANABE ,  Takahiro YAMADA ,  Mikito NOZAKI ,  Takuji HOSOI ,  Takayoshi SHIMURA

IPC分类号： H01L29/40 ,  H01L29/20 ,  H01L21/02 ,  H01L21/285

CPC分类号： H01L29/408 ,  H01L21/02241 ,  H01L21/02389 ,  H01L21/02483 ,  H01L21/0254 ,  H01L21/28008 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device (100) includes a base layer (10), an interface layer (20), and a deposition layer (30). The base layer (10) includes a nitride semiconductor that contains gallium. The interface layer (20) is adjacent to the base layer (10). The interface layer (20) contains gallium oxide. The deposition layer (30) is adjacent to the interface layer (20). The deposition layer (30) has a wider band gap than the interface layer (20). The interface layer (20) preferably has crystallinity. The interface layer (20) preferably contains α-phase Ga2O3.

公开(公告)号：US20180040710A1

公开(公告)日：2018-02-08

申请号：US15684498

申请日：2017-08-23

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ULVAC, Inc.

发明人： Vijay Narayanan ,  Yohei Ogawa ,  John Rozen

IPC分类号： H01L29/51 ,  H01L21/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/20 ,  H01L21/28 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/513 ,  H01L21/02043 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/02205 ,  H01L21/02241 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/28264 ,  H01L21/30612 ,  H01L29/0669 ,  H01L29/20 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7851

摘要： A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.

公开(公告)号：US09837521B2

公开(公告)日：2017-12-05

申请号：US14434674

申请日：2013-10-07

申请人： ROHM CO., LTD.

发明人： Kenji Yamamoto ,  Tetsuya Fujiwara ,  Minoru Akutsu ,  Ken Nakahara ,  Norikazu Ito

IPC分类号： H01L29/423 ,  H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/417 ,  H01L21/265 ,  H01L21/311 ,  H01L29/51 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/02694 ,  H01L21/2654 ,  H01L21/26586 ,  H01L21/28264 ,  H01L21/30621 ,  H01L21/31116 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/78

摘要： A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervenes therebetween.

公开(公告)号：US09679967B1

公开(公告)日：2017-06-13

申请号：US15282152

申请日：2016-09-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Takashi Ando ,  Kevin K. Chan ,  John Rozen ,  Jeng-Bang Yau ,  Yu Zhu

IPC分类号： H01L29/08 ,  H01L21/265 ,  H01L21/266 ,  H01L21/02 ,  H01L21/225 ,  H01L29/207

CPC分类号： H01L21/823418 ,  H01L21/02241 ,  H01L21/02546 ,  H01L21/0257 ,  H01L21/18 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/28575 ,  H01L21/3215 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/452 ,  H01L29/66007 ,  H01L29/66522 ,  H01L29/6659 ,  H01L29/66628

摘要： A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate. The method also includes forming a thin spacer surrounding the gate structure and forming a source/drain junction with a first doped III-V material at an upper surface of the III-V semiconductor substrate. The method also includes oxidizing a surface the source/drain forming an oxidation layer; removing natural oxides from the oxidation layer on a surface of the source/drain to expose ions of the first doped material at least at a surface of the source/drain. The method further includes applying a second doping to the source/drain to increase a doping concentration of the first doped III-V material, forming metal contacts at least at the second doped surface of the source/drain; and then annealing the contact.