公开(公告)号：US20240363716A1

公开(公告)日：2024-10-31

申请号：US18770929

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Wu-Wei TSAI ,  Chun-Chieh LU ,  Hai-Ching CHEN ,  Yu-Ming LIN ,  Sai-Hooi YEONG

IPC分类号： H01L29/49 ,  H01L21/02 ,  H01L21/443 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/4908 ,  H01L21/02233 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02565 ,  H01L21/443 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

摘要： A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

公开(公告)号：US20240250152A1

公开(公告)日：2024-07-25

申请号：US18623390

申请日：2024-04-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Xusheng Wu ,  Chang-Miao Liu ,  Huiling SHANG

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/66742 ,  H01L21/7624 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66787 ,  H01L29/78603 ,  H01L29/78696 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2253 ,  H01L21/26533 ,  H01L29/0673

摘要： A semiconductor structure includes a substrate, an oxide layer disposed over the substrate, a stack of semiconductor layers disposed over the oxide layer, and an epitaxial source/drain (S/D) feature disposed adjacent to the stack of semiconductor layers. A portion of the epitaxial S/D feature is horizontally surrounded by the oxide layer.

公开(公告)号：US20240250022A1

公开(公告)日：2024-07-25

申请号：US18594011

申请日：2024-03-04

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Hsih-Yang CHIU

IPC分类号： H01L23/525 ,  H01L21/02 ,  H01L27/08

CPC分类号： H01L23/5252 ,  H01L21/0223 ,  H01L21/02255 ,  H01L27/0802

摘要： A method of forming the electrical fuse matrix includes forming a seed layer on a plurality of bottom metal plates extending in a first direction; forming a plurality of poly-silicon cylinders on the seed layer; forming a spacer surrounding the plurality of poly-silicon cylinders and covering the seed layer; forming a plurality of hourglass-shaped trenches between the poly-silicon cylinders by removing a portion of the spacer; forming a plurality of anti-fuse structures in the hourglass-shaped trenches; and forming a plurality of top metal plates on the anti-fuse structures.

公开(公告)号：US12040241B2

公开(公告)日：2024-07-16

申请号：US17423150

申请日：2019-12-13

申请人： XIDIAN UNIVERSITY

发明人： Chen Liu ,  Yuming Zhang ,  Hongliang Lv

IPC分类号： H01L23/06 ,  C23C8/10 ,  C23C8/80 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455 ,  H01L21/02 ,  H01L21/48 ,  H01L21/52

CPC分类号： H01L23/06 ,  C23C8/10 ,  C23C16/345 ,  C23C16/402 ,  C23C16/45525 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/481 ,  H01L21/52

摘要： This disclosure provides a package structure for a semiconductor device, comprising a three-layer film consisting of a first SiO2 film, a Si3N4 film and a second SiO2 film stacked in this order, wherein the first SiO2 film is formed by a thermal oxidation process, the Si3N4 film is formed by a low pressure chemical vapor deposition process, and the second SiO2 film is formed by a low temperature atomic layer deposition process. This disclosure also provides a method for preparing the package structure for a semiconductor device.

公开(公告)号：US12009212B2

公开(公告)日：2024-06-11

申请号：US17510918

申请日：2021-10-26

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Kuo-Hui Su

IPC分类号： H01L21/033 ,  H01L21/02 ,  H01L21/3115

CPC分类号： H01L21/0338 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31155

摘要： A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.

公开(公告)号：US11985824B2

公开(公告)日：2024-05-14

申请号：US17084315

申请日：2020-10-29

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Jianzhong Wu ,  Jingjing Geng

IPC分类号： H01L27/11582 ,  H10B43/27 ,  H01L21/02

CPC分类号： H10B43/27 ,  H01L21/0223 ,  H01L21/02255

摘要： Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers on the substrate. The memory stack includes a core structure and a staircase structure. The staircase structure is on one side of the memory stack. The 3D memory device also includes a dummy channel structure extending vertically through the staircase structure. The dummy channel structure includes a plurality of sections along a vertical side of the dummy channel structure. The plurality of sections respectively interface with the interleaved conductive layers in the staircase structure. At least one of the plurality of sections includes a non-flat surface at an interface between the at least one of the plurality of sections and a corresponding conductive layer.

公开(公告)号：US11923441B2

公开(公告)日：2024-03-05

申请号：US17888894

申请日：2022-08-16

申请人： Applied Materials, Inc.

发明人： Steven C. H. Hung ,  Benjamin Colombeau ,  Andy Lo ,  Byeong Chan Lee ,  Johanes F. Swenberg ,  Theresa Kramer Guarini ,  Malcolm J. Bevan

IPC分类号： H01L29/66 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/455 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02 ,  H01L29/423

CPC分类号： H01L29/6681 ,  C23C8/02 ,  C23C8/16 ,  C23C8/80 ,  C23C16/45536 ,  C23C16/56 ,  C30B29/06 ,  C30B29/52 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L29/42392 ,  H01L29/6653

摘要： Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

公开(公告)号：US11923236B2

公开(公告)日：2024-03-05

申请号：US17931445

申请日：2022-09-12

申请人： Turun yliopisto

发明人： Pekka Laukkanen ,  Mikhail Kuzmin ,  Jaakko Mäkelä ,  Marjukka Tuominen ,  Marko Punkkinen ,  Antti Lahti ,  Kalevi Kokko ,  Juha-Pekka Lehtiö

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/762 ,  H01L23/31

CPC分类号： H01L21/7624 ,  H01L21/02238 ,  H01L21/02255 ,  H01L23/3171 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02271 ,  H01L21/0228

摘要： A method for forming a semiconductor structure comprising a silicon-on-insulator layer structure with crystalline silicon oxide SiOx as the insulator material comprises: providing a crystalline silicon substrate having a substantially clean deposition surface in a vacuum chamber; heating the silicon substrate to an oxidation temperature To in the range of 550 to 1200 ° C.; supplying, while keeping the silicon substrate in the oxidation temperature, with an oxidation pressure Po in the range of 1·10−8 to 1·10−4 mbar in the vacuum chamber, molecular oxygen O2 into the vacuum chamber with an oxygen dose Do in the range of 0.1 to 1000 Langmuir; whereby a crystalline silicon oxide layer with a thickness of at least two molecular layers is formed within the silicon substrate, between a crystalline silicon base layer and a crystalline silicon top layer. Related semiconductor structures are described.

公开(公告)号：US11917827B2

公开(公告)日：2024-02-27

申请号：US17648719

申请日：2022-01-24

申请人： Kioxia Corporation

发明人： Naoki Yasuda

IPC分类号： H01L27/1157 ,  H01L21/02 ,  H01L21/28 ,  H01L29/10 ,  H01L29/423 ,  H01L29/51 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： H10B43/35 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02326 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/518 ,  H10B43/10 ,  H10B43/27 ,  H01L21/02252 ,  H01L21/02255

摘要： According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.

公开(公告)号：US11908930B2

公开(公告)日：2024-02-20

申请号：US17404165

申请日：2021-08-17

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Namchil Mun ,  Shiang Yang Ong

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762

CPC分类号： H01L29/7816 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/76202 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66681

摘要： Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.