公开(公告)号：US12009212B2

公开(公告)日：2024-06-11

申请号：US17510918

申请日：2021-10-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/3115

CPC classification number: H01L21/0338 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31155

Abstract: A semiconductor structure includes a base layer with a top surface and a plurality of processed areas. A primary pattern is disposed on the top surface of the base layer, wherein the primary pattern has a pattern top surface, a processed area on the pattern top surface, and a sidewall, and the primary pattern has a first critical dimension, and the processed areas are on the part of the top surface of the base layer exposed by the primary pattern. A secondary pattern is disposed on the sidewall of the primary pattern, wherein the secondary pattern has a second critical dimension, and the second critical dimension is smaller than the first critical dimension.

公开(公告)号：US11756885B2

公开(公告)日：2023-09-12

申请号：US17533414

申请日：2021-11-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/5329

Abstract: The present application discloses a method for fabricating a semiconductor device with metal spacers. The method includes providing a substrate; forming a plurality of plugs above the substrate; forming a plurality of metal spacers above the plurality of plugs; and, forming a plurality of air gaps positioned between the plurality of plugs; wherein the step of forming wherein the plurality of metal spacers comprises forming a first set of metal spacers, forming a second set of metal spacers, forming a third set of metal spacers, and forming a fourth set of metal spacers; wherein the second set of metal spacers is formed between the first set of metal spacers and the third set of metal spacers, and the third set of metal spacers is formed between the second set of metal spacers and the fourth set of metal spacers.

公开(公告)号：US11638375B2

公开(公告)日：2023-04-25

申请号：US17550369

申请日：2021-12-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H10B12/00 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure provides a method for preparing a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature. The method includes forming an isolation member defining an active region in a substrate and a doped area in the active region; forming a gate structure in the substrate, wherein the gate structure divides the doped are into a first doped region and a second doped region; forming a bit line structure on the first doped region; forming an air gap adjacent to the bit line structure; forming a capacitor plug on the second doped region and a barrier layer on a sidewall of the capacitor plug; and forming a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer over the protruding portion and a second silicide layer on a sidewall of the barrier layer.

公开(公告)号：US12218053B2

公开(公告)日：2025-02-04

申请号：US18508575

申请日：2023-11-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535

Abstract: The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.

公开(公告)号：US11469182B2

公开(公告)日：2022-10-11

申请号：US17093977

申请日：2020-11-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768 ,  H01L27/108

Abstract: A semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate, and a second conductive layer disposed over the first conductive layer. The semiconductor device structure also includes a first conductive plug disposed between and electrically connecting the first conductive layer and the second conductive layer. The first conductive plug includes copper. The semiconductor device structure further includes a first lining layer surrounding the first conductive plug. The first lining layer includes manganese.

公开(公告)号：US11309245B2

公开(公告)日：2022-04-19

申请号：US16665350

申请日：2019-10-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/535

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having a plurality of contacts, a plurality of plugs positioned above the plurality of contacts, a plurality of metal spacers positioned above the plurality of plugs; and a plurality of air gaps respectively positioned between the plurality of metal spacers.

公开(公告)号：US12154788B2

公开(公告)日：2024-11-26

申请号：US17573160

申请日：2022-01-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/311

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

公开(公告)号：US11521926B2

公开(公告)日：2022-12-06

申请号：US17197770

申请日：2021-03-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/027 ,  H01L21/033 ,  H01L21/768

Abstract: The present disclosure relates to a semiconductor device structure with a serpentine conductive feature and a method for forming the semiconductor device structure. The semiconductor device structure includes a conductive pad disposed in a semiconductor substrate, and a first mask layer disposed over the semiconductor substrate. The semiconductor device structure also includes a second mask layer disposed over the first mask layer. The first mask layer and the second mask layer are made of different materials. The semiconductor device structure further includes a conductive feature penetrating through the first mask layer and the second mask layer to connect to the conductive pad. The conductive feature has a serpentine pattern in a top view.

公开(公告)号：US10978459B2

公开(公告)日：2021-04-13

申请号：US16561280

申请日：2019-09-05

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L27/108 ,  H01L27/11582 ,  H01L21/02 ,  H01L29/78 ,  H01L27/11565 ,  G11C7/18 ,  G11C5/02

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having an upper surface; a plurality of first bit line contacts contacting the upper surface of the substrate and a plurality of second bit line contacts contacting the upper surface of the substrate, wherein the plurality of first bit line contacts and the plurality of second bit line contacts are positioned at different levels along a first direction; an air gap disposed between the first bit line contact and the second bit line contact; a plurality of first bit lines respectively correspondingly positioned on the plurality of first bit line contacts; and a plurality of second bit lines respectively correspondingly positioned on the plurality of first bit line contacts. The top surfaces of the plurality of second bit line contacts and the top surfaces of the plurality of first bit lines are positioned at different levels along a second direction substantially perpendicular to the first direction.

公开(公告)号：US10937790B1

公开(公告)日：2021-03-02

申请号：US16540493

申请日：2019-08-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L29/06

Abstract: A semiconductor device includes a first bit line disposed over a semiconductor substrate. The semiconductor device also includes a capacitor contact and a dielectric structure disposed over the semiconductor substrate and adjacent to the first bit line. The capacitor contact, the dielectric structure and the first bit line are separated from one another by an air gap structure.