公开(公告)号：US12068371B2

公开(公告)日：2024-08-20

申请号：US17240027

申请日：2021-04-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun Hsiung Tsai ,  Ya-Yun Cheng ,  Shahaji B. More ,  Cheng-Yi Peng ,  Wei-Yang Lee ,  Kuo-Feng Yu ,  Yen-Ming Chen ,  Jian-Hao Chen

IPC分类号： H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/06 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/0217 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/36 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7851 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/266 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

摘要： A semiconductor device includes a substrate; an isolation structure over the substrate; a fin over the substrate and the isolation structure; a gate structure engaging a first portion of the fin; first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin; source/drain (S/D) features adjacent to the first sidewall spacers; and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride. The second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.

公开(公告)号：US20240047580A1

公开(公告)日：2024-02-08

申请号：US18167170

申请日：2023-02-10

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Yi TANG ,  Jianfeng XIAO

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7836 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66969

摘要： Embodiments of the disclosure provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a source doped region, a drain doped region, and a lightly doped region and an intrinsic region that are arranged adjacent to each other and located between the source doped region and the drain doped region. The lightly doped region is adjacent to the source doped region, and the intrinsic region is adjacent to the drain doped region. A doping concentration of the source doped region and the drain doped region is greater than a doping concentration of the lightly doped region.

公开(公告)号：US20230369491A1

公开(公告)日：2023-11-16

申请号：US18359156

申请日：2023-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/04 ,  H01L29/08 ,  H01L29/66 ,  H01L21/324 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L29/7833 ,  H01L21/02057 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66636 ,  H01L21/02532 ,  H01L21/324 ,  H01L29/66575 ,  H01L29/165 ,  H01L29/66628

摘要： The present disclosure relates to an integrated chip. The integrated chip includes a gate structure arranged over a substrate and a source/drain region arranged within the substrate along a side of the gate structure. The source/drain region includes a first layer lining interior sidewalls and a horizontally extending surface of the substrate, and a second layer lining interior sidewalls and a horizontally extending surface of the first layer. The first layer has a dopant with a first dopant concentration that continually decreases from an outermost sidewall of the first layer facing the substrate to one of the interior sidewalls of the first layer.

公开(公告)号：US20230369460A1

公开(公告)日：2023-11-16

申请号：US17835977

申请日：2022-06-09

申请人： United Microelectronics Corp.

发明人： Kuang-Hsiu Chen ,  Wei-Chung Sun ,  Chao Nan Chen ,  Chun-Wei Yu ,  Kuan Hsuan Ku ,  Shao-Wei Wang

IPC分类号： H01L29/66

CPC分类号： H01L29/66636 ,  H01L29/66575 ,  H01L29/66446 ,  H01L29/66795

摘要： Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.

公开(公告)号：US11749752B2

公开(公告)日：2023-09-05

申请号：US17110592

申请日：2020-12-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li

IPC分类号： H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/04 ,  H01L29/08 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/324 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/66628

摘要： The present disclosure relates to a method of forming a transistor device. The method may be performed by forming a gate structure onto a semiconductor substrate and forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure. One or more strain inducing materials are formed within the source/drain recess. The one or more strain inducing materials include a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the one or more strain inducing materials to a position above the bottommost surface. The bottommost surface contacts the semiconductor substrate.

公开(公告)号：US11728378B2

公开(公告)日：2023-08-15

申请号：US17210819

申请日：2021-03-24

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Poren Tang

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L21/764

CPC分类号： H01L29/0649 ,  H01L21/7682 ,  H01L29/41775 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66575 ,  H01L21/764 ,  H01L29/78

摘要： The present specification discloses a semiconductor device and a method for manufacturing same. In one implementation, the method may include: providing a semiconductor structure, wherein the semiconductor structure includes a substrate, a gate structure disposed on the substrate, initial spacer layers on side surfaces of two sides of the gate structure, and a first inter-layer dielectric layer covering the gate structure and the initial spacer layers; and the substrate includes a source and a drain respectively located on the two sides of the gate structure; etching the first inter-layer dielectric layer to form a source contact hole and a drain contact hole that expose a part of the initial spacer layer; removing the exposed part of the initial spacer layer to expose the side surface of the gate structure; forming a spacer structure layer on the exposed side surface of the gate structure; forming a source contact member and a drain contact member in the contact holes; selectively removing at least a part of the spacer structure layer to form an air gap; and forming a second inter-layer dielectric layer covering the air gap. In the present invention, an air gap spacer structure can be formed and parasitic capacitance is reduced.

公开(公告)号：US20190237543A1

公开(公告)日：2019-08-01

申请号：US15882285

申请日：2018-01-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun Hsiung Tsai ,  Ya-Yun Cheng ,  Shahaji B. More ,  Cheng-Yi Peng ,  Wei-Yang Lee ,  Kuo-Feng Yu ,  Yen-Ming Chen ,  Jian-Hao Chen

IPC分类号： H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L29/167 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/36

CPC分类号： H01L29/0847 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/30604 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7851

摘要： A method includes providing a structure having a substrate, a fin, and a gate structure; performing an implantation process to implant a dopant into the fin adjacent to the gate structure; and forming gate sidewall spacers and fin sidewall spacers. The method further includes performing a first etching process to recess the fin adjacent to the gate sidewall spacers while keeping at least a portion of the fin above the fin sidewall spacers. The method further includes performing another implantation process to implant the dopant into the fin and the fin sidewall spacers; and performing a second etching process to recess the fin adjacent to the gate sidewall spacers until a top surface of the fin is below a top surface of the fin sidewall spacers, resulting in a trench between the fin sidewall spacers. The method further includes epitaxially growing a semiconductor material in the trench.

公开(公告)号：US20190123182A1

公开(公告)日：2019-04-25

申请号：US16100908

申请日：2018-08-10

申请人： Renesas Electronics Corporation

发明人： Yoshiki YAMAMOTO

IPC分类号： H01L29/66 ,  H01L29/792 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11563

CPC分类号： H01L29/66833 ,  H01L21/0214 ,  H01L21/28017 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/0617 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/792

摘要： The reliability of a semiconductor device is improved. A first insulating film and a protective film are formed on a semiconductor substrate. The first insulating film and the protective film of a first region are selectively removed, and an insulating film is formed on the exposed semiconductor substrate. In a state where the first insulating film in a second region, a third region, and a fourth region is covered with the protective film, the semiconductor substrate is heat-treated in an atmosphere containing nitrogen, thereby introducing nitrogen to the interface between the semiconductor substrate and the second insulating film in the first region. In other words, a nitrogen introduction point is formed on the interface between the semiconductor substrate and the second insulating film. In this configuration, the protective film acts as an anti-nitriding film.

公开(公告)号：US20190115222A1

公开(公告)日：2019-04-18

申请号：US16219835

申请日：2018-12-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Keng-Ying LIAO ,  Chung-Bin TSENG ,  Po-Zen CHEN ,  Yi-Hung CHEN ,  Yi-Jie CHEN

IPC分类号： H01L21/3065 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/308 ,  H01L21/28 ,  H01L21/033 ,  H01L21/027 ,  H01L29/66

CPC分类号： H01L21/3065 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/31127 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

摘要： A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.

公开(公告)号：US10084062B2

公开(公告)日：2018-09-25

申请号：US15657401

申请日：2017-07-24

申请人： Hewlett-Packard Development Company, L.P.

发明人： Ning Ge ,  Leong Yap Chia ,  Pin Chin Lee ,  Jose Jehrome Rando

IPC分类号： H01L29/66 ,  H01L21/332

CPC分类号： H01L29/66575 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/78 ,  H05K2203/013

摘要： In some examples, a semiconductor device includes a substrate, a first doped region formed in the substrate, a second doped region around and spaced apart from the first doped region, and a channel between the first and second doped regions and formed using a gate ring on the substrate as a mask. A gate is formed over only a portion of the channel, the gate being a portion of the gate ring.