公开(公告)号：US11107923B2

公开(公告)日：2021-08-31

申请号：US16441337

申请日：2019-06-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kun-Mu Li ,  Heng-Wen Ting ,  Yen-Ru Lee ,  Hsueh-Chang Sung

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02 ,  H01L29/66

摘要： A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium concentration that is smaller than the second germanium concentration.

公开(公告)号：US11075120B2

公开(公告)日：2021-07-27

申请号：US16542578

申请日：2019-08-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kun-Mu Li ,  Heng-Wen Ting ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Chien-Wei Lee

IPC分类号： H01L21/82 ,  H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L29/78 ,  H01L21/3065

摘要： A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.

公开(公告)号：US10797173B2

公开(公告)日：2020-10-06

申请号：US16213049

申请日：2018-12-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L21/768 ,  H01L27/088 ,  H01L29/08 ,  H01L21/8238

摘要： An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.

公开(公告)号：US10084089B2

公开(公告)日：2018-09-25

申请号：US15695813

申请日：2017-09-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kun-Mu Li ,  Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Chii-Horng Li ,  Tze-Liang Lee

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/08

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834

摘要： An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

公开(公告)号：US10014411B2

公开(公告)日：2018-07-03

申请号：US15152260

申请日：2016-05-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsz-Mei Kwok ,  Kun-Mu Li ,  Hsueh-Chang Sung ,  Chii-Horng Li ,  Tze-Liang Lee

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L27/088 ,  H01L29/08 ,  H01L29/45 ,  H01L29/40 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3205 ,  H01L29/167 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/768

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.

公开(公告)号：US09583483B2

公开(公告)日：2017-02-28

申请号：US14017062

申请日：2013-09-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kun-Mu Li ,  Tsz-Mei Kwok ,  Hsueh-Chang Sung ,  Chii-Horng Li ,  Tze-Liang Lee

IPC分类号： H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834

摘要： An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

摘要翻译： 集成电路结构包括半导体衬底上的栅极堆叠以及延伸到半导体衬底中并且邻近栅极叠层的硅锗区域。 硅锗区域具有顶表面，顶表面的中心部分从顶表面的边缘部分凹陷以形成凹陷。 边缘部分在中心部分的相对侧上。

公开(公告)号：US09362360B2

公开(公告)日：2016-06-07

申请号：US14691435

申请日：2015-04-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsz-Mei Kwok ,  Kun-Mu Li ,  Hsueh-Chang Sung ,  Chii-Horng Li ,  Tze-Liang Lee

IPC分类号： H01L21/33 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L27/088 ,  H01L29/45 ,  H01L29/40 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/768

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.

公开(公告)号：US08815713B2

公开(公告)日：2014-08-26

申请号：US13671243

申请日：2012-11-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kuan-Yu Chen ,  Kun-Mu Li

IPC分类号： H01L21/20

CPC分类号： H01L21/823814 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/0843 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions.

摘要翻译： 一种方法包括在半导体衬底上形成栅极叠层，在半导体衬底中形成开口并且邻近栅叠层，并且执行第一外延以在第一开口中生长第一半导体层。 执行回蚀以减小第一半导体层的厚度。 执行第二外延以在第一半导体层上生长第二半导体层。 第一和第二半导体层具有不同的组成。

公开(公告)号：US20210050267A1

公开(公告)日：2021-02-18

申请号：US16542578

申请日：2019-08-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kun-Mu Li ,  Heng-Wen Ting ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Chien-Wei Lee

IPC分类号： H01L21/8234 ,  H01L21/308 ,  H01L21/3065 ,  H01L29/78 ,  H01L27/088

摘要： A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.

公开(公告)号：US10158016B2

公开(公告)日：2018-12-18

申请号：US15450265

申请日：2017-03-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsueh-Chang Sung ,  Tsz-Mei Kwok ,  Kun-Mu Li ,  Tze-Liang Lee ,  Chii-Horng Li

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8238

摘要： An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration.