公开(公告)号：US11967533B2

公开(公告)日：2024-04-23

申请号：US17355444

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Uei Jang ,  Shu-Yuan Ku ,  Shih-Yao Lin

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate that both extend along a first direction. The method includes forming a dielectric fin extending along the first direction and is disposed between the first and second semiconductor fins. The method includes forming a dummy gate structure extending along a second direction and straddling the first and second semiconductor fins and the dielectric fin. The method includes removing a portion of the dummy gate structure over the dielectric fin to form a trench by performing an etching process that includes a plurality of stages. Each of the plurality of stages includes a combination of anisotropic etching and isotropic etching such that a variation of a distance between respective inner sidewalls of the trench along the second direction is within a threshold.

公开(公告)号：US20240120209A1

公开(公告)日：2024-04-11

申请号：US18011837

申请日：2021-12-22

Applicant: Lam Research Corporation

Inventor： Nikhil Dole ,  Takumi Yanagawa ,  Eric A. Hudson ,  Merrett Wong ,  Aniruddha Joi

IPC: H01L21/311 ,  H01J37/32 ,  H01L21/3213 ,  H01L21/67

CPC classification number: H01L21/31116 ,  H01J37/32082 ,  H01J37/32449 ,  H01L21/32137 ,  H01L21/67069 ,  H01L21/67253 ,  H01J2237/327 ,  H01J2237/3341

Abstract: A method for etching a stack is described. The method includes etching a first nitrogen-containing layer of the stack by applying a non-metal gas and discontinuing the application of the non-metal gas upon determining that a first oxide layer is reached. The first oxide layer is under the first nitrogen-containing layer. The method further includes etching the first oxide layer by applying a metal-containing gas. The application of the metal-containing gas is discontinued upon determining that a second nitrogen-containing layer will be reached. The second nitrogen-containing layer is situated under the first oxide layer. The method includes etching the second nitrogen-containing layer by applying the non-metal gas.

公开(公告)号：US20240072142A1

公开(公告)日：2024-02-29

申请号：US18218751

申请日：2023-07-06

Applicant: SEMES CO., LTD.

Inventor： Thomas Jongwan KWON ,  Hae-won CHOI ,  Yunsang KIM

IPC: H01L29/423 ,  H01L21/3213

CPC classification number: H01L29/4236 ,  H01L21/32137

Abstract: Provided is a method of manufacturing a semiconductor device, the method including steps of providing a semiconductor substrate having one or more trenches, forming a gate insulating layer on the semiconductor substrate inside the trenches, and forming a buried gate electrode layer on the gate insulating layer to at least partially fill the trenches, wherein the step of forming the buried gate electrode layer includes a step of repeating a unit cycle a plurality of times, the unit cycle including an atomic layer deposition (ALD) process for forming a conductive layer on the gate insulating layer to serve as the buried gate electrode layer, and an atomic layer etching (ALE) process for preferentially etching portions of the conductive layer formed near the trenches and portions of the conductive layer formed on upper ends of the trenches over other portions of the conductive layer inside the trenches.

公开(公告)号：US11888042B2

公开(公告)日：2024-01-30

申请号：US18094484

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L27/06 ,  H01L29/423 ,  H01L21/3213 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/27 ,  H01L29/792 ,  H01L29/51

CPC classification number: H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/27 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20240014213A1

公开(公告)日：2024-01-11

申请号：US18205090

申请日：2023-06-02

Applicant: Silergy Semiconductor Technology (Hangzhou) LTD

Inventor： Zheng Lv ,  Xunyi Song ,  Chihsen Huang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/033

CPC classification number: H01L27/0922 ,  H01L21/823857 ,  H01L21/82385 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42376 ,  H01L21/32137 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  H01L29/66681

Abstract: A method of manufacturing a semiconductor device structure can include: forming a first gate dielectric layer on a first region of a semiconductor substrate, and forming a second gate dielectric layer on a second region of the semiconductor substrate; forming a conductive layer on the first and second gate dielectric layers; forming a barrier layer on the conductive layer; patterning the barrier layer to form a barrier pattern; etching the conductive layer to form first and second gates using the barrier pattern as a mask; forming a photolithography pattern on the semiconductor substrate, where the photolithography pattern exposes the well implantation area of the first region and a portion of the barrier pattern on the first gate; forming a well region in the well implantation area using the lithography pattern and the exposed barrier pattern as masks; and removing the photolithography pattern and the barrier pattern.

公开(公告)号：US20230411462A1

公开(公告)日：2023-12-21

申请号：US18460290

申请日：2023-09-01

Applicant: Applied Materials, Inc.

Inventor： Akhil Singhal ,  Allison Yau ,  Sang-Jin Kim ,  Zeqiong Zhao ,  Zhijun Jiang ,  Deenesh Padhi ,  Ganesh Balasubramanian

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L29/40114 ,  H01L21/31116 ,  H01L21/32137 ,  H01L29/42324

Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å.

公开(公告)号：US20230386857A1

公开(公告)日：2023-11-30

申请号：US18447810

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yun-Jui HE ,  Chih-Teng LIAO

IPC: H01L21/3213 ,  G03F1/70 ,  G06F30/39

CPC classification number: H01L21/32137 ,  G03F1/70 ,  G06F30/39 ,  H01L21/32139

Abstract: Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.

公开(公告)号：US20230369140A1

公开(公告)日：2023-11-16

申请号：US18314226

申请日：2023-05-09

Applicant: NEXPERIA B.V.

Inventor： Steven Peake ,  MD Imran Siddiqui

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L22/26 ,  H01L21/02238 ,  H01L21/32137 ,  H01L29/407 ,  H01L29/7813 ,  H01L29/401 ,  H01L29/66734

Abstract: A method of creating a vertical semiconductor device, the method includes the steps of performing a LOCal Oxidation of Silicon, LOCOS, process in a vertical trench of a semiconductor material so that oxide material is formed inside the vertical trench, and ledges are formed by the oxide material, inside the vertical trench, as a result of the LOCOS process, so that a lower region of reduced lateral distance is formed between the oxide material, at a base of the trench, depositing the trench with polysilicon and etching the polysilicon downward up to the oxide material using interferometric end point detection, so that polysilicon remains in the lower region.

公开(公告)号：US20230352563A1

公开(公告)日：2023-11-02

申请号：US18342146

申请日：2023-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Cheng-Po Chau ,  Yun Chen Teng

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/3205 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/32137 ,  H01L27/0924 ,  H01L21/02645 ,  H01L21/32055 ,  H01L21/02359 ,  H01L21/823864 ,  H01L21/823821 ,  H01L21/02664

Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.

公开(公告)号：US11804379B2

公开(公告)日：2023-10-31

申请号：US17405305

申请日：2021-08-18

Applicant: Tokyo Electron Limited

Inventor： Taku Gohira ,  Michiko Nakaya

IPC: H01L21/311 ,  H01L21/3213 ,  H01J37/32 ,  H01L21/02

CPC classification number: H01L21/31116 ,  H01J37/32724 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/0217 ,  H01L21/02164

Abstract: An etching method of forming, on a substrate having a base film; a stacked film in which a first film and a second film are alternately stacked on the base film; and a mask on the stacked film, a recess in the stacked film through the mask by using plasma includes preparing the substrate; and etching the stacked film until the recess of the stacked film reaches the base film by plasma formed from a gas containing hydrogen, fluorine and carbon, while maintaining a substrate temperature equal to or less than 15° C.