公开(公告)号：US12087841B2

公开(公告)日：2024-09-10

申请号：US17850850

申请日：2022-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yi-Lun Chen ,  Bau-Ming Wang ,  Chun-Hsiung Lin

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02592 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/76834

摘要： A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin; forming a helmet layer lining the gate structure and the semiconductor fin; etching the helmet layer to remove portions of the helmet layer from opposite sidewalls of the gate structure, wherein the remaining helmet layer comprises a first remaining portion on a top surface of the gate structure and a second remaining portion on a top surface of the semiconductor fin; forming a spacer layer covering the gate structure, wherein the spacer layer is in contact with the first remaining portion and the second remaining portion of the remaining helmet layer; etching the spacer layer and the remaining helmet layer to form gate spacers, wherein each of the gate spacers has a stepped sidewall; and forming source/drain epitaxy structures on opposite sides of the gate structure.

公开(公告)号：US12057495B2

公开(公告)日：2024-08-06

申请号：US18326682

申请日：2023-05-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yao-Sheng Huang ,  Hung-Chang Sun ,  I-Ming Chang ,  Zi-Wei Fang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/08 ,  H01L29/78 ,  H01L21/306

CPC分类号： H01L29/66795 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/02675 ,  H01L21/31116 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/30604

摘要： A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.

公开(公告)号：US12040176B2

公开(公告)日：2024-07-16

申请号：US17706408

申请日：2022-03-28

申请人： Tokyo Electron Limited

发明人： Shihsheng Chang ,  Andrew Metz ,  Yun Han ,  Minjoon Park ,  Ya-Ming Chen

IPC分类号： H01L21/02 ,  H10B43/20

CPC分类号： H01L21/02115 ,  H01L21/02172 ,  H01L21/02488 ,  H01L21/02592 ,  H10B43/20

摘要： A semiconductor device structure includes a dielectric layer formed on a silicon substrate, an amorphous carbon layer (ACL) formed on the dielectric layer, and a charge dissipation layer formed between the ACL and the dielectric layer. The charge dissipation layer is formed from a material having a resistivity lower than the resistivity of the ACL. Methodologies to fabricate the semiconductor device structure are also disclosed and include forming the dielectric layer on the silicon substrate, forming the charge dissipation layer on the dielectric layer, and forming the ACL on the charge dissipation layer. Alternative semiconductor device structures and fabrication methodologies are also disclosed.

公开(公告)号：US20240128160A1

公开(公告)日：2024-04-18

申请号：US18378060

申请日：2023-10-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Zhaoxu SHEN ,  Yang LI ,  Junwei GUO ,  Yue YIN

IPC分类号： H01L23/48 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/02592 ,  H01L21/28088 ,  H01L21/76802

摘要： A semiconductor structure includes a substrate; a first electrode layer over the substrate; a dielectric layer on a sidewall surface of the first electrode layer; and a second electrode layer over the substrate. The first electrode layer, the dielectric layer, and the second electrode layer are arranged in a direction parallel to a surface of the substrate.

公开(公告)号：US11903200B2

公开(公告)日：2024-02-13

申请号：US17362624

申请日：2021-06-29

申请人： SK hynix Inc.

发明人： Yu Jeong Lee ,  Dae Hwan Yun ,  Gil Bok Choi

IPC分类号： H10B43/27 ,  H10B41/27 ,  H01L23/31 ,  H01L29/04 ,  H01L29/16 ,  H01L21/02

CPC分类号： H10B43/27 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L23/3171 ,  H01L29/04 ,  H01L29/16

摘要： A semiconductor memory device may include a core pillar extended in a vertical direction, a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering the other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region abutting the first region, and a channel passivation layer formed in the first region of the channel layer and abutting the core pillar.

公开(公告)号：US20240038532A1

公开(公告)日：2024-02-01

申请号：US18258380

申请日：2021-12-22

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Matthew CHARLES ,  Guy FEUILLET ,  Carole PERNEL

IPC分类号： H01L21/02

CPC分类号： H01L21/0254 ,  H01L21/02592 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/0243 ,  H01L33/007

摘要： A method for obtaining at least one nitride layer based upon a III-N material includes the successive steps of providing a stack having a support substrate and a plurality of pads, each pad including at least one basal section and one germination section carried by the basal section; modifying the basal section so as to form a modified basal section having a lower rigidity that the basal section before modification; and epitaxially growing a crystallite from the top of at least some of the pads of an assembly and continuing the epitaxial growth so as to form the nitride layer on pads on the assembly.

公开(公告)号：US20240015968A1

公开(公告)日：2024-01-11

申请号：US18370543

申请日：2023-09-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kohji KANAMORI ,  Shinhwan KANG

IPC分类号： H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H10B43/10 ,  H10B43/40 ,  H10B43/50

CPC分类号： H10B43/27 ,  H01L23/5226 ,  H01L23/528 ,  H01L21/02667 ,  H01L21/31144 ,  H01L29/40117 ,  H01L21/31111 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02636 ,  H01L21/31116 ,  H10B43/10 ,  H10B43/40 ,  H10B43/50

摘要： A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.

公开(公告)号：US11735416B2

公开(公告)日：2023-08-22

申请号：US17027331

申请日：2020-09-21

申请人： Micron Technology, Inc.

发明人： Ashonita A. Chavan ,  Durai Vishak Nirmal Ramaswamy ,  Michael Mutch ,  Sameer Chhajed

IPC分类号： H01L21/02 ,  H01L27/12 ,  H01L29/786 ,  H01L21/762

CPC分类号： H01L21/02592 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/762 ,  H01L27/1222 ,  H01L27/1285 ,  H01L29/78642

摘要： A method includes forming a first amorphous material, forming a second amorphous material over and in contact with the first material, removing a portion of the second material and the first material to form pillars, and exposing the materials to a temperature between a crystallization temperature of the first material and a crystallization temperature of the second material. The first material and the second material each comprise at least one element selected from the group consisting of silicon and germanium. The second material exhibits a crystallization temperature different than a crystallization temperature of the first material. Semiconductor structures, memory devices, and systems are also disclosed.

公开(公告)号：US11695071B2

公开(公告)日：2023-07-04

申请号：US17159594

申请日：2021-01-27

申请人： Micron Technology, Inc.

发明人： Manuj Nahar ,  Michael Mutch

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L21/02 ,  H01L29/04 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/7827 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L29/04 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/36 ,  H01L29/66666

摘要： A transistor comprises a top source/drain region, a bottom source/drain region, and a channel region vertically between the top and bottom source/drain regions. A gate is operatively laterally-adjacent the channel region. The top source/drain region, the bottom source/drain region, and the channel region respectively have crystal grains and grain boundaries between immediately-adjacent of the crystal grains. At least one of the bottom source/drain region and the channel region has an internal interface there-within between the crystal grains that are above the internal interface and the crystal grains that are below the internal interface. At least some of the crystal grains that are immediately-above the internal interface physically contact at least some of the crystal grains that are immediately-below the internal interface. All of the grain boundaries that are between immediately-adjacent of the physically-contacting crystal grains that are immediately-above and that are immediately-below the interface align relative one another. The internal interface comprises at least one of (a) and (b), where (a): conductivity-modifying dopant concentration immediately-above the internal interface is lower than immediately-below the internal interface and (b): a laterally-discontinuous insulative oxide. Other embodiments, including method, are disclosed.

公开(公告)号：US11658030B2

公开(公告)日：2023-05-23

申请号：US16713311

申请日：2019-12-13

申请人： ASM IP Holding B.V.

发明人： Tom Blomberg ,  Chiyu Zhu

IPC分类号： H01L21/02 ,  H01L21/28 ,  C23C16/40 ,  C23C16/455

CPC分类号： H01L21/02565 ,  C23C16/401 ,  C23C16/407 ,  C23C16/45523 ,  C23C16/45527 ,  H01L21/0228 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/28194 ,  H01L21/02592

摘要： Methods for forming a doped metal oxide film on a substrate by cyclical deposition are provided. In some embodiments, methods may include contacting the substrate with a first reactant comprising a metal halide source, contacting the substrate with a second reactant comprising a hydrogenated source and contacting the substrate with a third reactant comprising an oxide source. In some embodiments, related semiconductor device structures may include a doped metal oxide film formed by cyclical deposition processes.