公开(公告)号：US10014211B2

公开(公告)日：2018-07-03

申请号：US15684722

申请日：2017-08-23

申请人： Micron Technology, Inc.

发明人： David H. Wells

IPC分类号： H01L21/20 ,  H01L21/764 ,  H01L21/02

CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

摘要： Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US09947591B2

公开(公告)日：2018-04-17

申请号：US15352960

申请日：2016-11-16

申请人： IMEC VZW

发明人： Clement Merckling ,  Guillaume Boccardi

IPC分类号： H01L21/8238 ,  H01L27/06 ,  H01L21/8258 ,  H01L21/02 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L21/823807 ,  H01L21/02543 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

公开(公告)号：US20180082907A1

公开(公告)日：2018-03-22

申请号：US15825826

申请日：2017-11-29

申请人： IMEC VZW

发明人： Clement Merckling ,  Guillaume Boccardi

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/8258 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L21/823807 ,  H01L21/02543 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

摘要： A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

公开(公告)号：US09842964B2

公开(公告)日：2017-12-12

申请号：US15304447

申请日：2015-04-15

申请人： OSRAM Opto Semiconductors GmbH

发明人： Joachim Hertkorn ,  Werner Bergbauer

IPC分类号： H01L33/00 ,  H01L33/12 ,  H01L21/02 ,  C30B25/04 ,  C30B25/18 ,  C30B29/40 ,  H01L21/78 ,  H01L31/0304 ,  H01L31/0392 ,  H01L31/18 ,  H01L33/32 ,  H01S5/02

CPC分类号： H01L33/12 ,  C30B25/04 ,  C30B25/183 ,  C30B25/186 ,  C30B29/403 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/0265 ,  H01L21/02664 ,  H01L21/7813 ,  H01L31/03048 ,  H01L31/0392 ,  H01L31/1852 ,  H01L31/1856 ,  H01L31/1892 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/32 ,  H01S5/0206 ,  H01S5/0213 ,  H01S5/0217

摘要： A method for producing a semiconductor layer sequence is disclosed. In an embodiment the includes growing a first nitridic semiconductor layer at the growth side of a growth substrate, growing a second nitridic semiconductor layer having at least one opening on the first nitridic semiconductor layer, removing at least pail of the first nitridic semiconductor layer through the at least one opening in the second nitridic semiconductor layer, growing a third nitridic semiconductor layer on the second nitridic semiconductor layer, wherein the third nitridic semiconductor layer covers the at least one opening at least in places in such a way that at least one cavity free of a semiconductor material is present between the growth substrate and a subsequent semiconductor layers and removing the growth substrate.

公开(公告)号：US09818826B2

公开(公告)日：2017-11-14

申请号：US14519230

申请日：2014-10-21

申请人： Sensor Electronic Technology, Inc.

发明人： Maxim S. Shatalov ,  Rakesh Jain ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC分类号： H01L29/15 ,  H01L33/00 ,  H01L33/12 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L21/02

CPC分类号： H01L29/151 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/0075 ,  H01L33/12

摘要： A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.

公开(公告)号：US09806228B2

公开(公告)日：2017-10-31

申请号：US15389479

申请日：2016-12-23

申请人： Sensor Electronic Technology, Inc.

发明人： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC分类号： H01L27/15 ,  H01L31/072 ,  H01L33/06 ,  H01L33/32 ,  H01L33/24 ,  H01L33/12 ,  H01L21/02 ,  H01L29/778 ,  H01L33/22 ,  H01L29/20 ,  H01L29/51

CPC分类号： H01L33/06 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/2003 ,  H01L29/518 ,  H01L29/7786 ,  H01L33/12 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0083 ,  H01L2933/0091

摘要： A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US09786548B2

公开(公告)日：2017-10-10

申请号：US14712219

申请日：2015-05-14

申请人： Micron Technology, Inc.

发明人： David H. Wells

IPC分类号： H01L21/336 ,  H01L21/764 ,  H01L21/20 ,  H01L21/02

CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

摘要： Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

公开(公告)号：US09773906B2

公开(公告)日：2017-09-26

申请号：US15002078

申请日：2016-01-20

申请人： Wei-E Wang ,  Mark S. Rodder ,  Ganesh Hedge ,  Christopher Bowen

发明人： Wei-E Wang ,  Mark S. Rodder ,  Ganesh Hedge ,  Christopher Bowen

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/764 ,  H01L21/02 ,  H01L21/308 ,  H01L29/04

CPC分类号： H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/3081 ,  H01L21/764 ,  H01L29/045 ,  H01L29/161

摘要： Methods of forming a layer of silicon germanium include forming an epitaxial layer of Si1-xGex on a silicon substrate, wherein the epitaxial layer of Si1-xGex has a thickness that is less than a critical thickness, hc, at which threading dislocations form in Si1-xGex on silicon; etching the epitaxial layer of Si1-xGex to form Si1-xGex pillars that define a trench in the epitaxial layer of Si1-xGex, wherein the trench has a height and a width, wherein the trench has an aspect ratio of height to width of at least 1.5; and epitaxially growing a suspended layer of Si1-xGex from upper portions of the Si1-xGex pillars, wherein the suspended layer defines an air gap in the trench beneath the suspended layer of Si1-xGex.

公开(公告)号：US20170250253A1

公开(公告)日：2017-08-31

申请号：US15250638

申请日：2016-08-29

申请人： STMICROELECTRONICS S.R.L.

发明人： Fabrizio Fausto Renzo Toia ,  Claudio Contiero ,  Elisabetta Pizzi ,  Simone Dario Mariani

IPC分类号： H01L29/10 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/1087 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02664 ,  H01L21/3247 ,  H01L21/74 ,  H01L21/743 ,  H01L23/535 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/7802

摘要： A semiconductor device comprising: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.

公开(公告)号：US20170236704A1

公开(公告)日：2017-08-17

申请号：US15504634

申请日：2014-09-18

申请人： Intel Corporation

发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/04 ,  H01L21/8252 ,  H01L29/16 ,  H01L29/78 ,  H01L29/267 ,  H01L27/06 ,  H01L29/778

CPC分类号： H01L21/0265 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02521 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7851

摘要： III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.