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公开(公告)号：US10394652B2
公开(公告)日：2019-08-27
申请号：US14930351
申请日：2015-11-02
申请人： SK hynix Inc.
发明人： Gil Bok Choi , Suk Kwang Park , Min Sang Park
摘要： A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.
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公开(公告)号：US11894431B2
公开(公告)日：2024-02-06
申请号：US17231515
申请日：2021-04-15
申请人： SK hynix Inc.
发明人： Dae Hwan Yun , Gil Bok Choi
CPC分类号： H01L29/408 , H10B43/27
摘要： The present technology includes a memory device. The memory device includes a stack structure including word lines and a select line, a vertical hole vertically penetrating the stack structure, and a memory layer, a channel layer, and a plug, sequentially formed along an inner side surface of the vertical hole. The plug includes a material layer having a fixed negative charge.
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公开(公告)号：US10146442B2
公开(公告)日：2018-12-04
申请号：US15642606
申请日：2017-07-06
申请人： SK hynix Inc.
发明人： Sung Ho Kim , Min Sang Park , Yong Seok Suh , Kyong Taek Lee , Gil Bok Choi
IPC分类号： G06F3/06
摘要： Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.
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公开(公告)号：US09977712B2
公开(公告)日：2018-05-22
申请号：US14966571
申请日：2015-12-11
申请人： SK hynix Inc.
发明人： Min Sang Park , Suk Kwang Park , Yun Bong Lee , Sung Hoon Cho , Gil Bok Choi
CPC分类号： G06F11/1068 , G11C29/52 , G11C2029/0411
摘要： The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.
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公开(公告)号：US11903200B2
公开(公告)日：2024-02-13
申请号：US17362624
申请日：2021-06-29
申请人： SK hynix Inc.
发明人： Yu Jeong Lee , Dae Hwan Yun , Gil Bok Choi
CPC分类号： H10B43/27 , H01L21/02164 , H01L21/02238 , H01L21/02532 , H01L21/02592 , H01L21/02667 , H01L23/3171 , H01L29/04 , H01L29/16
摘要： A semiconductor memory device may include a core pillar extended in a vertical direction, a channel layer having a first region covering a portion of a side surface of the core pillar and a second region covering the other portion of the side surface of the core pillar and a bottom surface of the core pillar, the second region abutting the first region, and a channel passivation layer formed in the first region of the channel layer and abutting the core pillar.
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公开(公告)号：US11812613B2
公开(公告)日：2023-11-07
申请号：US17211460
申请日：2021-03-24
申请人： SK hynix Inc.
发明人： Dae Hwan Yun , Gil Bok Choi
摘要： The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.
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公开(公告)号：US11521684B2
公开(公告)日：2022-12-06
申请号：US17308583
申请日：2021-05-05
申请人： SK hynix Inc.
发明人： Gil Bok Choi , Dae Hwan Yun
摘要： A memory device, and a method of operating the same, includes a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells. The memory device also includes a peripheral circuit configured to perform a sensing operation of sensing selected memory cells coupled to a selected word line selected from among the plurality of word lines. The memory device further includes control logic configured to control the peripheral circuit apply a turn-on voltage to a block word line coupled to the selected word line when the sensing operation is terminated and when potentials of the plurality of word lines are increased due to a recovery operation for channels of the plurality of memory cells after the plurality of word lines have been discharged.
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公开(公告)号：US11790979B2
公开(公告)日：2023-10-17
申请号：US17364137
申请日：2021-06-30
申请人： SK hynix Inc.
发明人： Gil Bok Choi , Dae Hwan Yun
IPC分类号： G11C11/408 , G11C7/10 , G11C11/4096 , G11C11/4074
CPC分类号： G11C11/4085 , G11C7/1063 , G11C11/4074 , G11C11/4096
摘要： The present disclosure relates to an electronic device. A memory device according to the present disclosure includes a memory block coupled to a plurality of local word lines, a peripheral circuit configured to couple the plurality of local word lines to a plurality of global word lines and configured to perform an operation on the memory block, and a control logic configured to control the peripheral circuit to cause or increase a leakage current of the pass switch circuit to discharge potential levels of the plurality of local word lines when the memory device enters a ready state after the operation.
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公开(公告)号：US11315944B2
公开(公告)日：2022-04-26
申请号：US16661291
申请日：2019-10-23
申请人： SK hynix Inc.
发明人： Moon Sik Seo , Gil Bok Choi
IPC分类号： H01L27/11582 , H01L27/11521 , H01L27/11551
摘要： The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.
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公开(公告)号：US10353776B2
公开(公告)日：2019-07-16
申请号：US14930351
申请日：2015-11-02
申请人： SK hynix Inc.
发明人： Gil Bok Choi , Suk Kwang Park , Min Sang Park
摘要： A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.
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