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公开(公告)号：US10394652B2
公开(公告)日：2019-08-27
申请号：US14930351
申请日：2015-11-02
申请人： SK hynix Inc.
发明人： Gil Bok Choi , Suk Kwang Park , Min Sang Park
摘要： A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.
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公开(公告)号：US10353776B2
公开(公告)日：2019-07-16
申请号：US14930351
申请日：2015-11-02
申请人： SK hynix Inc.
发明人： Gil Bok Choi , Suk Kwang Park , Min Sang Park
摘要： A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.
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公开(公告)号：US09859014B2
公开(公告)日：2018-01-02
申请号：US15212559
申请日：2016-07-18
申请人： SK hynix Inc.
发明人： Min Sang Park , Sung Ho Kim , Kyong Taek Lee , Yun Bong Lee , Gil Bok Choi
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3454
摘要： There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on the memory cell array. The control logic may control the peripheral circuit to program the memory cell array. The one or more programs are configured to be executed by the control logic. The programs may include an instruction for pre-programming one or more memory cells to be programmed to one or more target program states to have threshold voltage distributions lower than the target program state.
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公开(公告)号：US10418116B2
公开(公告)日：2019-09-17
申请号：US15630667
申请日：2017-06-22
申请人： SK hynix Inc.
发明人： Min Sang Park , Myoung Kwan Cho
摘要： A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes a plurality of memory blocks. The control logic groups the memory blocks, determines driving voltages to be respectively applied to the groups, and applies each of the determined driving voltages to memory blocks included in a corresponding group to control the operation of the memory cell array.
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公开(公告)号：US10037805B2
公开(公告)日：2018-07-31
申请号：US15173357
申请日：2016-06-03
申请人： SK hynix Inc.
发明人： Giulio Martinozzi , Min Sang Park , Sang Jo Lee
CPC分类号： G11C16/10 , G06F3/0604 , G06F3/0632 , G06F3/0679 , G11C11/5628 , G11C16/0483 , G11C16/32
摘要： A method is provided for programming a non-volatile memory having a plurality of word lines, the method comprising: applying a pass voltage to a selected word line among the plurality of word lines; and applying one of first and second program voltages to the selected word line by increasing the pass voltage, wherein the applying of one of the first and second program voltages increases the pass voltage with a single increment.
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公开(公告)号：US09576668B2
公开(公告)日：2017-02-21
申请号：US14970755
申请日：2015-12-16
申请人： SK hynix Inc.
发明人： Sung Ho Kim , Min Sang Park , Kyong Taek Lee
CPC分类号： G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/30
摘要： The semiconductor device includes a memory block including programmed pages and non-programmed pages, a peripheral circuit configured to perform a read operation of the memory block, and a control circuit configured to control the peripheral circuit so that a read voltage is applied to a word line coupled to a selected page among the pages for the read operation, a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation, and a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation.
摘要翻译： 该半导体器件包括一个包括编程页面和非编程页面的存储器块，被配置为执行该存储器块的读取操作的外围电路以及一个控制电路，该控制电路被配置为控制该外围电路，使得读取电压被施加到一个字 线耦合到用于读取操作的页面中的所选页面，第一通过电压被施加到与未被选择用于读取操作的页面之中的编程页面耦合的字线，以及低于第一通过电压的第二通过电压 被应用于在未被选择用于读取操作的页面中耦合到非编程页面的字线。
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公开(公告)号：US10146442B2
公开(公告)日：2018-12-04
申请号：US15642606
申请日：2017-07-06
申请人： SK hynix Inc.
发明人： Sung Ho Kim , Min Sang Park , Yong Seok Suh , Kyong Taek Lee , Gil Bok Choi
IPC分类号： G06F3/06
摘要： Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.
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公开(公告)号：US09977712B2
公开(公告)日：2018-05-22
申请号：US14966571
申请日：2015-12-11
申请人： SK hynix Inc.
发明人： Min Sang Park , Suk Kwang Park , Yun Bong Lee , Sung Hoon Cho , Gil Bok Choi
CPC分类号： G06F11/1068 , G11C29/52 , G11C2029/0411
摘要： The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.
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公开(公告)号：US10296226B2
公开(公告)日：2019-05-21
申请号：US16177109
申请日：2018-10-31
申请人： SK hynix Inc.
发明人： Sung Ho Kim , Min Sang Park , Yong Seok Suh , Kyong Taek Lee , Gil Bok Choi
摘要： Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.
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公开(公告)号：US10224102B2
公开(公告)日：2019-03-05
申请号：US15835898
申请日：2017-12-08
申请人： SK hynix Inc.
发明人： Gil Bok Choi , Sung Hoon Cho , Sung Ho Kim , Min Sang Park , Kyong Taek Lee , Myoung Kwan Cho
摘要： A semiconductor memory device may include a control logic. The control logic may be coupled to bit lines through a read and write (read/write) circuit and to word lines. The control logic is configured to determine a duration of an activation time of a strobe signal for the read/write circuit.
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