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公开(公告)号：US12094552B2
公开(公告)日：2024-09-17
申请号：US18374026
申请日：2023-09-28
发明人： Sehwan Park , Jinyoung Kim , Ilhan Park , Kyoman Kang , Sangwan Nam
CPC分类号： G11C29/50004 , G11C7/1039 , G11C7/1045 , G11C7/1057 , G11C7/1084 , G11C8/18 , G11C16/28 , G11C29/44 , G11C2029/1202 , G11C2029/1204
摘要： A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.
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公开(公告)号：US20240290413A1
公开(公告)日：2024-08-29
申请号：US18431279
申请日：2024-02-02
发明人： Dongxiang Liao , Tomer Tzvi Eliash
摘要： A boot-up read pattern data structure is maintained. Each entry of the boot-up read pattern data structure comprises a boot-up read pattern associated with a respective power cycle event and a dummy boot-up read pattern flag. The dummy boot-up read pattern flag indicates that the boot-up read pattern has been consecutively used during boot-up. Storing, in a new entry of the boot-up read pattern data structure, a current boot-up read pattern associated with a respective power cycle event for each power cycle event. The current boot-up read pattern with a previous boot-up read pattern associated with a latest entry of the boot-up pattern data structure is compared. A dummy boot-up read pattern flag of the new entry is updated responsive to the comparing the current boot-up read pattern and the previous boot-up read pattern.
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公开(公告)号：US20240290395A1
公开(公告)日：2024-08-29
申请号：US18360634
申请日：2023-07-27
CPC分类号： G11C16/28 , G11C16/0433 , G11C16/08 , G11C16/24
摘要： Technology is disclosed herein for a storage system that reduces the Icc during open block reads. A lower than nominal voltage may be applied to the bit lines during open block reads, which reduces Icc. A nominal bit line voltage may be used during closed block reads. The lower than nominal bit line voltage may be combined with using a lower than nominal read pass voltage (Vread) to unprogrammed word lines during the open block read. The lower than nominal Vread has a lower magnitude than a nominal Vread used during a closed block read. Combining the lower than nominal bit line voltage with the lower than nominal Vread to unprogrammed word lines further reduces Icc during open block reads. The ramp rate of Vread may be relaxed (made slower) during at least some open block reads in combination with the lower than nominal bit line voltage.
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公开(公告)号：US20240274206A1
公开(公告)日：2024-08-15
申请号：US18385073
申请日：2023-10-30
发明人： Yongseok KWON , Jaeduk YU , Sangsoo PARK , Jonghoon PARK , Jauang YOON
摘要： The present disclosure provides nonvolatile memory devices including high-voltage switch circuits and methods of controlling the same. In some embodiments, a nonvolatile memory device includes a voltage generator configured to generate a switching source voltage, a plurality of high-voltage switch circuits grouped into a plurality of switching groups and configured to generate a plurality of switch control signals based on the switching source voltage, a conductive path configured to transfer the switching source voltage from the voltage generator to the plurality of high-voltage switch circuits, a plurality of high-voltage switches configured to transfer high voltages based on the plurality of switch control signals, and a control circuit configured to control transition timing of the plurality of switch control signals independently with respect to each of the plurality of switching groups.
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公开(公告)号：US20240274202A1
公开(公告)日：2024-08-15
申请号：US18431886
申请日：2024-02-02
摘要： A memory sub-system having a memory device with a plurality of cells and a processing device operatively coupled to the memory device, the processing device to perform the operations of: responsive to detecting a power off event, programming, to a predefined logical state, a dummy subset of the plurality of cells; responsive to detecting a power-up event, determining a voltage shift associated with the dummy subset of the plurality of cells; and identifying, based on the voltage shift, a voltage offset bin shift corresponding to a voltage offset bin associated with a specified subset of the plurality of cells.
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公开(公告)号：US20240153569A1
公开(公告)日：2024-05-09
申请号：US17981462
申请日：2022-11-06
发明人： Wen-Chiao Ho
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/24 , G11C16/28
摘要： A flash memory device and a program method thereof are provided. The flash memory device includes a memory array, a first global bit line, and a sense amplifying device. The memory array includes a first memory block having a plurality of first memory cells. In a leakage current detection operation, the sense amplifying device detects a leakage current generated by the first memory cells on the first global bit line to obtain leakage current simulation information. In a program operation, the sense amplifying device provides a reference current according to the leakage current simulation information, and compares a sensing current generated by a selected memory cell in the first memory cells on the first global bit line with the reference current to perform a program verification.
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7.发明授权公开(公告)号：US11894062B2
公开(公告)日：2024-02-06
申请号：US17398718
申请日：2021-08-10
CPC分类号： G11C16/14 , G11C16/08 , G11C16/102 , G11C16/24 , G11C16/28 , G11C16/34 , G11C16/3409 , G11C16/3445
摘要： A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.
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8.发明公开公开(公告)号：US20240029803A1
公开(公告)日：2024-01-25
申请号：US18375869
申请日：2023-10-02
发明人： Eli Harari
IPC分类号： G11C16/34 , H01L21/28 , G11C16/04 , G11C16/10 , G11C16/26 , G11C16/28 , H01L29/66 , H01L27/06 , H01L29/792 , H10B43/27 , H10B43/40 , G11C11/56
CPC分类号： G11C16/3431 , H01L29/40117 , G11C16/0416 , G11C16/0466 , G11C16/0491 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3427 , H01L29/66833 , H01L27/0688 , H01L29/7926 , H10B43/27 , H10B43/40 , G11C11/5628 , G11C11/5635 , G11C16/0483 , H05K999/99 , H10B43/10
摘要： Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.
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公开(公告)号：US11875851B2
公开(公告)日：2024-01-16
申请号：US18080524
申请日：2022-12-13
申请人： KIOXIA CORPORATION
发明人： Hiroshi Maejima
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/28 , G11C16/3427 , G11C16/32
摘要： A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
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公开(公告)号：US11869587B2
公开(公告)日：2024-01-09
申请号：US17495423
申请日：2021-10-06
CPC分类号： G11C13/004 , G11C7/1051 , G11C11/2255 , G11C11/2273 , G11C16/0483 , G11C16/28 , G11C7/14 , G11C2013/0054
摘要： Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.
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