-
公开(公告)号：US20240203490A1
公开(公告)日：2024-06-20
申请号：US18590692
申请日：2024-02-28
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C2013/0054
摘要： A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.
-
公开(公告)号：US11869587B2
公开(公告)日：2024-01-09
申请号：US17495423
申请日：2021-10-06
CPC分类号： G11C13/004 , G11C7/1051 , G11C11/2255 , G11C11/2273 , G11C16/0483 , G11C16/28 , G11C7/14 , G11C2013/0054
摘要： Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.
-
公开(公告)号：US20230335191A1
公开(公告)日：2023-10-19
申请号：US17720957
申请日：2022-04-14
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C2013/0054
摘要： A variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. The access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. A reference current can be provided from the access line biasing circuit to the sense circuit. Additional devices, systems, and methods are discussed.
-
公开(公告)号：US11715508B2
公开(公告)日：2023-08-01
申请号：US17387301
申请日：2021-07-28
发明人： Hyun Yoo Lee , Suryanarayana B. Tatapudi , Huy T. Vo , Ferdinando Bedeschi , Umberto Di Vincenzo , Riccardo Muzzetto
IPC分类号： G11C11/22 , G11C11/4094 , G11C11/4091
CPC分类号： G11C11/2273 , G11C11/221 , G11C11/4091 , G11C11/4094
摘要： Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.
-
公开(公告)号：US11705211B2
公开(公告)日：2023-07-18
申请号：US17415646
申请日：2020-07-14
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/22 , G11C16/26 , G11C16/3404 , G11C29/52
摘要： The present disclosure relates to a method for accessing an array of memory cells, including storing a set of user data in a plurality of memory cells, storing, in a portion of the array, additional information representative of a voltage difference between a first threshold voltage and a second threshold voltage of the memory cells programmed to a first logic state, applying to the array a read voltage to activate a first group of memory cells corresponding to a preset number of memory cells, determining that the first group of memory cells has been activated based on applying the read voltage, wherein the read voltage is equal to the first threshold voltage when the first group of memory cells has been activated, and based on the additional data information, applying the voltage difference to the array to activate a second group of memory cells programmed to the first logic state.
-
公开(公告)号：US11694748B2
公开(公告)日：2023-07-04
申请号：US17716716
申请日：2022-04-08
CPC分类号： G11C13/004 , G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2013/0045
摘要： A method, a circuit, and a system for reading memory cells. The method may include: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second polarity to one or more of said plurality of the memory cells; applying at least a third voltage with the first polarity to one or more of said plurality of the memory cells; detecting electrical responses of memory cells to the first voltage, the second voltage, and the third voltage; and determining a logic state of respective memory cells based on the electrical responses of the memory cells to the first voltage, the second voltage, and the third voltage.
-
公开(公告)号：US20230207004A1
公开(公告)日：2023-06-29
申请号：US16971053
申请日：2020-05-18
发明人： Marco Sforzin , Umberto Di Vincenzo
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0038 , G11C13/0097 , G11C2013/0054 , G11C2213/71
摘要： Devices, systems and methods for adaptively controlling a reset current of a memory cell are described. A system comprises: a mirror circuit with one branch coupled with a top electrode of the memory cell and the other branch coupled with one end of a resistive reference, and wherein a bottom electrode of the memory cell is coupled to a reference potential, the other end of the resistive reference is provided with a first electric potential; a control circuit; and a feedback circuit for feeding an electric potential to the top electrode of the memory cell.
-
公开(公告)号：US11538526B2
公开(公告)日：2022-12-27
申请号：US17162693
申请日：2021-01-29
摘要： The present disclosure includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.
-
公开(公告)号：US11527279B2
公开(公告)日：2022-12-13
申请号：US16908299
申请日：2020-06-22
摘要： Methods, systems, and devices for a read algorithm for a memory device are described. When performing a read operation, the memory device may access a memory cell to retrieve a value stored by the memory cell. The memory device may compare a set of reference voltages with a signal output by the memory cell based on accessing the memory cell. Thus, the memory device may determine a set of candidate values stored by the memory cell, where each candidate value is associated with one of the reference voltages. The memory device may determine and output the value stored by the memory cell based on determining the set of candidate values. In some cases, the memory device may determine the value stored by the memory cell based on performing an error control operation on each of the set of candidate values to detect a quantity of errors within each candidate value.
-
公开(公告)号：US20220319618A1
公开(公告)日：2022-10-06
申请号：US17415646
申请日：2020-07-14
摘要： The present disclosure relates to a method for accessing an array of memory cells, including storing a set of user data in a plurality of memory cells, storing, in a portion of the array, additional information representative of a voltage difference between a first threshold voltage and a second threshold voltage of the memory cells programmed to a first logic state, applying to the array a read voltage to activate a first group of memory cells corresponding to a preset number of memory cells, determining that the first group of memory cells has been activated based on applying the read voltage, wherein the read voltage is equal to the first threshold voltage when the first group of memory cells has been activated, and based on the additional data information, applying the voltage difference to the array to activate a second group of memory cells programmed to the first logic state.
-
-
-
-
-
-
-
-
-
搜索结果
175 条记录 (耗时 0.035 秒)
