公开(公告)号：US12210749B2

公开(公告)日：2025-01-28

申请号：US18357948

申请日：2023-07-24

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Shay Fux ,  Sagie Goldenberg ,  Amotz Yagev

IPC: G06F13/16 ,  G06F3/06

Abstract: A memory system includes a memory device including an array of storage transistors for storing data where the storage transistors are organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, and a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize the number of active write requests that are addressed to different memory banks of the memory device.

公开(公告)号：US12189982B2

公开(公告)日：2025-01-07

申请号：US18453490

申请日：2023-08-22

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Robert D. Norman

IPC: G06F3/06

Abstract: A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In one embodiment, a memory system includes a set of memory modules of quasi-volatile memory circuits interconnected to a memory controller and having a set of memory ports. The memory system includes a first processor port, a second processor port, and one or more DIMM interface ports to be coupled to respective processors for providing access to the set of memory modules. In another embodiment, an artificial intelligence (AI) computing system includes a set of memory modules of quasi-volatile memory circuits interconnected to a memory controller and an arithmetic function block performing multiply and accumulate functionalities using data stored in the memory modules. The set of memory modules are accessed to perform read, write and erase memory operations in a rotating manner in each computing cycle.

公开(公告)号：US20240347109A1

公开(公告)日：2024-10-17

申请号：US18629205

申请日：2024-04-08

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Masahiro Yoshihara ,  Takashi Hirotani

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/08 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B43/10 ,  H10B43/27 ,  H10B51/10 ,  H10B51/20

CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C16/08 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B43/10 ,  H10B43/27 ,  H10B51/10 ,  H10B51/20

Abstract: A memory circuit includes an array of thin-film ferroelectric memory transistors formed by an array of NOR memory strings intersecting with local word line structures with global word lines arranged orthogonal to the array of NOR memory strings and aligned with a set of local word line structures provided across multiple stacks of NOR memory strings. The memory circuit includes a word line select transistor associated with each local word line structure to isolate each local word line structure from the associated global word line. The word line select transistor, when activated, selectively couples a selected local word line structure to the associated global word line. Remaining local word line structures associated with the same global word line remain disconnected and therefore not selected. In this manner, parasitic capacitance on the global word line is reduced and unintended disturb to other unselected memory transistors is also reduced.

公开(公告)号：US11937424B2

公开(公告)日：2024-03-19

申请号：US17458029

申请日：2021-08-26

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Eli Harari

IPC: H10B43/20

CPC classification number: H10B43/20

Abstract: A thin-film storage transistor formed in a memory array above a planar surface of a semiconductor substrate, includes (a) first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate; (b) a first semiconductor layer of a first conductivity having an opening therein; (c) second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer; (d) a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer; and (e) a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer, wherein the first, second and third semiconductor layers are each provided as a planar layer of materials between the first and second dielectric layers. In this configuration, the first, second and third semiconductor layers and the first conductor provide a channel region, a drain region, a source region and a gate electrode of the thin-film storage transistor.

公开(公告)号：US11923341B2

公开(公告)日：2024-03-05

申请号：US17467011

申请日：2021-09-03

Applicant: Sunrise Memory Corporation

Inventor： Khandker Nazrul Quader ,  Robert Norman ,  Frank Sai-keung Lee ,  Christopher J. Petti ,  Scott Brad Herner ,  Siu Lung Chan ,  Sayeef Salahuddin ,  Mehrdad Mofidi ,  Eli Harari

IPC: H01L25/065 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0802 ,  G06N3/02 ,  H01L25/00 ,  G11C16/04

CPC classification number: H01L25/0657 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/1068 ,  G06F12/0802 ,  G06N3/02 ,  H01L25/50 ,  G06F2212/60 ,  G06F2212/72 ,  G11C16/0483 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

公开(公告)号：US20240062838A1

公开(公告)日：2024-02-22

申请号：US18497402

申请日：2023-10-30

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Raul Adrian Cernea

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/26 ,  G11C16/14 ,  G11C16/0466

Abstract: A method is for ensuring data integrity in memory pages includes: dividing the memory pages into a predetermined number of refresh groups; and for each write operation to be performed on a selected memory page: (a) selecting one of the refresh groups; (b) reading data from the memory pages of the selected refresh group; and (d) concurrently (i) performing the write operation on the selected memory page, and (ii) writing back the data read into the memory pages of the selected refresh group.

公开(公告)号：US20240045615A1

公开(公告)日：2024-02-08

申请号：US18357948

申请日：2023-07-24

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Shay Fux ,  Sagie Goldenberg ,  Amotz Yagev

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0611 ,  G06F3/0679

Abstract: A memory system includes a memory device including an array of storage transistors for storing data where the storage transistors are organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, and a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize the number of active write requests that are addressed to different memory banks of the memory device.

公开(公告)号：US20230371266A1

公开(公告)日：2023-11-16

申请号：US18156959

申请日：2023-01-19

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Minori Kajimoto ,  Takashi Hirotani ,  Masahiro Yoshihara

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/30 ,  H01L23/528 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B51/20 ,  H01L23/5283 ,  H01L29/66742 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7869 ,  H10B51/10 ,  H10B51/30

Abstract: A memory device includes a stacked body of alternately arranged conductor-including layers and insulating films in the first direction and pillar bodies within the stacked body. Each pillar body includes first and second conductive pillars and an insulator pillar located between the first conductive pillar and the second conductive pillar. Each conductor-including layer includes a semiconductor member, an electrode film and a ferroelectric layer provided between the semiconductor member and the electrode film. The semiconductor members in the multiple conductor-including layers are separated from each other in the first direction.

公开(公告)号：US20230368843A1

公开(公告)日：2023-11-16

申请号：US18225879

申请日：2023-07-25

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli HARARI

IPC: G11C16/04 ,  H01L21/02 ,  G11C11/56 ,  G11C16/10 ,  H01L29/423 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L21/768 ,  H01L29/66 ,  H01L29/16 ,  H01L29/06 ,  H01L29/786 ,  H01L29/51 ,  H01L21/3213 ,  H01L29/04 ,  G11C16/34 ,  G11C16/28 ,  H01L21/28 ,  G11C16/26 ,  H01L29/792 ,  H01L27/06

CPC classification number: G11C16/0466 ,  H01L21/02164 ,  H01L21/0217 ,  G11C11/5635 ,  G11C16/0491 ,  G11C16/10 ,  H01L29/4234 ,  G11C16/0416 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/1037 ,  H01L21/02532 ,  H01L21/76892 ,  H01L29/66833 ,  H01L29/16 ,  H01L29/0649 ,  H01L29/78642 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6675 ,  H01L21/02595 ,  H01L21/32133 ,  H01L28/00 ,  H10B43/10 ,  H10B43/35 ,  H01L29/04 ,  G11C16/3427 ,  H10B43/27 ,  G11C16/28 ,  G11C16/0483 ,  H01L29/40117 ,  G11C16/26 ,  H01L29/7926 ,  H10B43/40 ,  H01L27/0688 ,  G11C11/5628

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

公开(公告)号：US11749344B2

公开(公告)日：2023-09-05

申请号：US17394249

申请日：2021-08-04

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/04 ,  H01L23/528 ,  G11C16/28 ,  H01L29/08 ,  H01L29/16 ,  H01L29/04 ,  H01L29/06 ,  H01L29/786 ,  G11C16/10 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/423 ,  H01L21/28 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  H01L27/06 ,  H01L29/792 ,  H01L49/02 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0466 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32133 ,  H01L21/76892 ,  H01L23/528 ,  H01L27/0688 ,  H01L28/00 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6675 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.