公开(公告)号：US12205654B2

公开(公告)日：2025-01-21

申请号：US17690713

申请日：2022-03-09

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Takayuki Inoue ,  Jiacen Guo

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: The memory device includes a plurality of memory cells which are arranged in an array. The memory device further includes a plurality of bit lines that are coupled with the memory cells and a controller. The controller is configured to program the memory cells from an erased data state to three programmed data states in a programming operation that includes three programming pulses and zero verify operations using different patterns to dictate the application of inhibit voltages to the bit lines during each of the three programming pulses. The patterns include two pre-established patterns and additional patterns that are derived from the pre-established patterns using logic operations.

公开(公告)号：US12198765B2

公开(公告)日：2025-01-14

申请号：US17750938

申请日：2022-05-23

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Chin-Yi Chen ,  Deepanshu Dutta

IPC: G11C5/14 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.

公开(公告)号：US12176037B2

公开(公告)日：2024-12-24

申请号：US17955878

申请日：2022-09-29

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Wei Cao ,  Jiacen Guo

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

Abstract: In a multi-tiered non-volatile memory structure that can perform operations on sub-blocks, performance of the different tiers/sub-blocks is made consistent by using different word line to word line pitches in the different tiers/sub-blocks.

公开(公告)号：US12057175B2

公开(公告)日：2024-08-06

申请号：US17715647

申请日：2022-04-07

Applicant: SanDisk Technologies LLC

Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Kou Tei ,  Deepanshu Dutta ,  Hiroyuki Mizukoshi ,  Jiahui Yuan ,  Xiang Yang

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459 ,  G11C11/5621 ,  G11C11/5671

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.

公开(公告)号：US20240212767A1

公开(公告)日：2024-06-27

申请号：US18225248

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102

Abstract: The memory device includes a memory block with an array of memory cells arranged word lines. The memory device also includes control circuitry that is configured to program final data into a selected word line in a multi-pass programming operation that includes a first pass and a second pass. In the first pass, the control circuitry is configured to program the memory cells of the selected word line to foggy data and program parity data in the memory device. The parity data includes three possible data states. Prior to the second pass, the control circuitry is configured to read the foggy data and the parity data and reconstruct the final data from the foggy data and the parity data. In the second pass, the control circuitry is configured to program the memory cells of the selected word line from the foggy data to the final data.

公开(公告)号：US20240203511A1

公开(公告)日：2024-06-20

申请号：US18221649

申请日：2023-07-13

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Peng Zhang ,  Xiang Yang ,  Yanli Zhang

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102

Abstract: The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.

公开(公告)号：US20240194278A1

公开(公告)日：2024-06-13

申请号：US18360327

申请日：2023-07-27

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/26

Abstract: Technology is disclosed herein for a memory system that includes one or more control circuits configured to connect to a three-dimensional memory structure that includes word lines, with each word line connected to a word line driver at one end. The one or more control circuits are configured to, in a program verify operation, sense memory cells of a first region of a selected word line for a first sense time and sense memory cells of a second region of the selected word line for a second sense time while applying a program-verify voltage to the selected word line. The first region is closer to the word line driver than the second region.

公开(公告)号：US20240192873A1

公开(公告)日：2024-06-13

申请号：US18220682

申请日：2023-07-11

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Wei Cao ,  Jiacen Guo

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F3/0604

Abstract: A storage device is disclosed herein. The storage device comprises a non-volatile memory, where the non-volatile memory includes a block of 3N wordlines partitioned into a plurality of sub-blocks. The plurality of sub-blocks include an upper sub-block of a first subset of the block of 3N wordlines, a lower sub-block of a second subset of the block of 3N wordlines, and a middle sub-block of a third subset of the block of 3N wordlines. Further, the storage device comprises control circuitry coupled to the block of 3N wordlines and configured to: perform a program operation in a normal order programming sequence on the upper sub-block; perform a program operation in a reverse order programming sequence on the lower sub-block; and perform a program operation in the reverse order programming sequence on the middle sub-block.

公开(公告)号：US20240161828A1

公开(公告)日：2024-05-16

申请号：US18357450

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Wei Cao ,  Jiacen Guo

IPC: G11C16/08 ,  G06F12/02 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/08 ,  G06F12/0246 ,  G11C16/10 ,  G11C16/16 ,  G06F2212/7201

Abstract: A non-volatile memory includes a plurality of non-volatile memory cells arranged in blocks. Each block includes multiple sub-blocks that can be independently erased and programmed. A control circuit is connected to the non-volatile memory cells. The control circuit is configured to independently erase and program sub-blocks of a same block. The control circuit is configured to only allow one sub-block per block to be open at a time.

公开(公告)号：US11972818B2

公开(公告)日：2024-04-30

申请号：US17841343

申请日：2022-06-15

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/26

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages targeted for each of the memory cells during a program-verify portion of a program operation. The control means is also configured to trim the program verify voltages for each of the data states for a grouping of the memory cells based on quantities of the memory cells having the threshold voltage crossing over between the data states in crossovers in a verify level trimming process.