公开(公告)号：US20240322845A1

公开(公告)日：2024-09-26

申请号：US18680900

申请日：2024-05-31

Applicant: KIOXIA CORPORATION

Inventor： Riki SUZUKI ,  Toshikatsu HIDA ,  Osamu TORII ,  Hiroshi YAO ,  Kiyotaka IWASAKI

IPC: H03M13/35 ,  G06F3/06 ,  G06F11/10 ,  G11B20/18 ,  G11C7/10 ,  G11C29/04 ,  G11C29/52 ,  H03M13/29

CPC classification number: H03M13/35 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G11C29/52 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2957 ,  G11B20/1833 ,  G11C7/1006 ,  G11C2029/0411

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

公开(公告)号：US12046284B2

公开(公告)日：2024-07-23

申请号：US18076304

申请日：2022-12-06

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Bastien Giraud ,  Valentin Gherman ,  Samuel Evain

IPC: G11C13/00 ,  G11C29/42 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C13/0069 ,  G11C29/42 ,  G11C29/52 ,  G06F11/1048 ,  G06F11/1068 ,  G11C13/004 ,  G11C2013/0083 ,  G11C2029/0411

Abstract: An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

公开(公告)号：US11979152B2

公开(公告)日：2024-05-07

申请号：US17181973

申请日：2021-02-22

Applicant: Intel Corporation

Inventor： Chang Kian Tan ,  Chee Hak Teh

IPC: H03K19/17 ,  G06F11/10 ,  G11C7/10 ,  G11C11/418 ,  G11C11/419 ,  G11C29/52 ,  H03K19/17736 ,  H03K19/1776 ,  G11C8/06 ,  G11C29/04

CPC classification number: H03K19/17744 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/1015 ,  G11C11/418 ,  G11C11/419 ,  G11C29/52 ,  H03K19/1776 ,  G11C7/106 ,  G11C7/1087 ,  G11C8/06 ,  G11C2029/0411

Abstract: An integrated circuit may include integrated memory that is formed from a chain of memory blocks. Each memory block may have configurable input and output circuits. The configurable input and output circuits may be interposed between memory circuitry such as a memory array from circuitry external to the memory circuitry. The configurable input and output circuits may have upstream and downstream memory block connection ports. In such a way, configurable input and output circuits in a first memory block may pass control and address signals and data to configurable input and output circuits in a second memory block. By using the configurable input and output circuits, the integrated memory in the integrated circuit may operate to accommodate large bandwidth flows without using the general routing fabric of the integrated circuit.

公开(公告)号：US11967364B2

公开(公告)日：2024-04-23

申请号：US18203511

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G06F11/10 ,  G11C7/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C11/4093 ,  G06F11/1048 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20240126475A1

公开(公告)日：2024-04-18

申请号：US18490357

申请日：2023-10-19

Applicant: Lodestar Licensing Group, LLC

Inventor： George Pax ,  Jonathan Scott Parry

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02 ,  G11C5/04 ,  G11C5/14 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/00 ,  G11C16/32 ,  G11C29/00 ,  G11C29/52

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0685 ,  G06F3/0688 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G11C5/04 ,  G11C5/141 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/005 ,  G11C16/32 ,  G11C29/52 ,  G11C29/883 ,  G06F2212/1032 ,  G06F2212/7202 ,  G11C2029/0411

Abstract: Apparatus and methods are provided for operating a non-volatile memory module. In an example, a method can include filling a first plurality of pages of a first non-volatile memory with first data from a first data lane that includes a first volatile memory device, and filling a second plurality of pages of the first non-volatile memory device with second data from a second data lane that includes a second volatile memory device. In certain examples, the first plurality of pages does not include data from the second data lane.

公开(公告)号：US11914481B2

公开(公告)日：2024-02-27

申请号：US18154500

申请日：2023-01-13

Applicant: Netlist, Inc.

Inventor： Scott H. Milton ,  Jeffrey C. Solomon ,  Kenneth S. Post

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/07 ,  G11C16/34 ,  G11C29/42 ,  G11C29/44 ,  G11C29/04

CPC classification number: G06F11/1458 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0793 ,  G11C16/349 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.

公开(公告)号：US11854658B2

公开(公告)日：2023-12-26

申请号：US17696818

申请日：2022-03-16

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  David Wang

IPC: G11C7/10 ,  G06F11/10 ,  G06F11/07 ,  G11C29/52 ,  G11C29/04 ,  G11C5/04

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/1006 ,  G06F11/1008 ,  G11C5/04 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

公开(公告)号：US11837284B2

公开(公告)日：2023-12-05

申请号：US18056587

申请日：2022-11-17

Applicant: Kioxia Corporation

Inventor： Masanobu Shirakawa ,  Takayuki Akamine

IPC: G11C11/10 ,  G06F11/10 ,  H03M13/29 ,  H03M13/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C11/5642 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C29/52 ,  H03M13/2906 ,  G11C2029/0411 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

公开(公告)号：US11822428B2

公开(公告)日：2023-11-21

申请号：US17991799

申请日：2022-11-21

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C11/00 ,  G06F11/10 ,  G11C29/52 ,  G11C29/02 ,  G11C11/56 ,  G11C16/26 ,  H03M13/11 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  H03M13/1102 ,  G11C2029/0411

Abstract: An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

公开(公告)号：US11789796B2

公开(公告)日：2023-10-17

申请号：US17843237

申请日：2022-06-17

Applicant: Ovonyx Memory Technology, LLC

Inventor： Wayne Kinney ,  Gurtej S. Sandhu

IPC: G06F11/07 ,  G11C29/04 ,  G11C11/16 ,  G11C29/02

CPC classification number: G06F11/0751 ,  G06F11/0727 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1677 ,  G11C29/021 ,  G11C2029/0411

Abstract: This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresistive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from the memory cells, a self-reference read can be performed from at least one of the memory cells. For instance, the condition can indicate that data read from the memory cells is uncorrectable via decoding of error correction codes (ECC). Selectively performing self-reference reads can reduce power consumption and/or latency associated with reading from the memory compared to always performing self-reference reads.