公开(公告)号：US12198755B2

公开(公告)日：2025-01-14

申请号：US18488517

申请日：2023-10-17

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Takayuki Akamine

IPC: G11C11/10 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/52 ,  H03M13/00 ,  H03M13/29 ,  G11C29/04

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

公开(公告)号：US11837284B2

公开(公告)日：2023-12-05

申请号：US18056587

申请日：2022-11-17

Applicant: Kioxia Corporation

Inventor： Masanobu Shirakawa ,  Takayuki Akamine

IPC: G11C11/10 ,  G06F11/10 ,  H03M13/29 ,  H03M13/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C11/5642 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C29/52 ,  H03M13/2906 ,  G11C2029/0411 ,  G11C2211/5642 ,  G11C2211/5643

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

公开(公告)号：US11557339B2

公开(公告)日：2023-01-17

申请号：US17343426

申请日：2021-06-09

Applicant: Kioxia Corporation

Inventor： Masanobu Shirakawa ,  Takayuki Akamine

IPC: G11C11/10 ,  G06F11/10 ,  H03M13/29 ,  H03M13/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/52 ,  G11C29/04

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

公开(公告)号：US11289167B2

公开(公告)日：2022-03-29

申请号：US17104564

申请日：2020-11-25

Applicant: KIOXIA CORPORATION

Inventor： Takayuki Akamine ,  Masanobu Shirakawa ,  Tokumasa Hara

IPC: G11C7/22 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C16/32 ,  G11C29/44

Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.