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公开(公告)号：US20240331787A1
公开(公告)日：2024-10-03
申请号：US18618456
申请日：2024-03-27
CPC分类号： G11C29/021 , G11C29/52
摘要： Various example embodiments relate to a capacitor action-based start-up circuit for bandgap reference (BGR) generation. The start-up circuit comprises a start-up capacitor connected to a VBG node of a BGR sub-circuit. The start-up capacitor determines if a state of operation of the BGR sub-block is one of normal, and failure. The start-up circuit comprises an output transistor connected to an NB node of the BGR. The output transistor charges the NB node to maintain normal operation of the BGR sub-block, if the state of operation of the BGR sub-block is failure, thereby facilitating dynamic behavior.
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公开(公告)号：US20240321373A1
公开(公告)日：2024-09-26
申请号：US18448274
申请日：2023-08-11
发明人： Narasimhan Trichy , Andrew Prosory
CPC分类号： G11C29/021 , G01R31/64
摘要： A data storage device includes a non-volatile memory device, a capacitor bank, and a power regulator electrically coupled to the capacitor bank and configured to provide power to the non-volatile memory device. The data storage device further includes a controller configured to discharge the capacitor bank from a first voltage to a second voltage at a first constant current and determine a first discharge time, controller is further configured to discharge the capacitor bank from the first voltage to the second voltage at a second constant current and determine a second discharge time. A voltage holdup time of the capacitor bank is then determined based on at least the first discharge time and the second discharge time.
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公开(公告)号：US20240296897A1
公开(公告)日：2024-09-05
申请号：US18660002
申请日：2024-05-09
发明人： Melissa I. Uribe
IPC分类号： G11C29/02 , G11C11/4076 , G11C11/4099 , H03K19/20
CPC分类号： G11C29/022 , G11C11/4076 , G11C11/4099 , G11C29/021 , H03K19/20
摘要： Methods, systems, and devices for techniques for determining an interface connection status are described. A system may include an interface between a host device and a memory device. The host device may transmit to the memory device first data in a pattern over a first set of transmission lines of the interface. The host device may also transmit to the memory device second data in the pattern over a second set of transmission lines of the interface. The memory device may compare the first data and the second data, and based on the comparison, send an indication of a connection status of the interface to the host device.
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公开(公告)号：US12080366B2
公开(公告)日：2024-09-03
申请号：US17854638
申请日：2022-06-30
发明人： Kangseok Lee , Geunyeong Yu , Seonghyeog Choi , Hongrak Son , Youngjun Hwang
CPC分类号： G11C29/52 , G11C29/021 , G11C29/022
摘要： In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.
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公开(公告)号：US20240274211A1
公开(公告)日：2024-08-15
申请号：US18583510
申请日：2024-02-21
发明人： Yoav Weinberg , Evgeni Bassin
CPC分类号： G11C29/021 , G11C5/144 , G11C29/028
摘要： Methods, systems, and devices for voltage detection for managed memory systems are described. In some cases, a memory system may include circuitry to monitor one or more supply voltages to the memory system or voltages generated by the memory system to determine whether a voltage rises above an operational range. In some cases, an overvoltage detector may include an undervoltage detector that has been tuned or manufactured to have a higher threshold than an undervoltage detector used to determine whether a voltage has fallen below the operational range. Accordingly, the memory system may monitor a voltage using an undervoltage detector having a threshold corresponding to a lower bound or lower operation point of the operational range of the monitored voltage and an overvoltage detectors having a threshold corresponding to the upper bound or upper operational point of the operational range.
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公开(公告)号：US20240194258A1
公开(公告)日：2024-06-13
申请号：US18586174
申请日：2024-02-23
发明人： Marco Sforzin , Paolo Amato , Innocenzo Tortorelli
CPC分类号： G11C13/0033 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C29/021 , G11C29/12005
摘要： A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.
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7.发明授权公开(公告)号：US11977750B2
公开(公告)日：2024-05-07
申请号：US17852103
申请日：2022-06-28
IPC分类号： G06F11/00 , G06F3/06 , G06F11/07 , G06F11/10 , G06F11/20 , G11C16/30 , G11C29/02 , G11C16/04
CPC分类号： G06F3/0625 , G06F3/0655 , G06F3/0679 , G06F11/0793 , G06F11/1048 , G06F11/2015 , G11C16/30 , G11C29/021 , G11C16/0483
摘要： Disclosed are systems and methods detecting and isolating faulty hold-up capacitors and performing corrective actions for a data storage device. A hardware circuit is coupled to a micro-controller and non-volatile memory dies. The method includes, at the hardware circuit: providing a back-up power for the non-volatile memory dies and the micro-controller; and detecting whether a hold-up capacitor of the hardware circuit is faulty and isolating the hold-up capacitor in accordance with a detection that the hold-up capacitor is faulty. The method also includes, at the micro-controller: obtaining a status of an interface coupled to the hardware circuit; determining a status of the hardware circuit based on the status of the interface; and performing a corrective action for the data storage device in accordance with a determination that the status of hardware circuit corresponds to one or more faulty hold-up capacitors.
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公开(公告)号：US11915750B2
公开(公告)日：2024-02-27
申请号：US17862391
申请日：2022-07-11
发明人： Marco Sforzin , Paolo Amato , Innocenzo Tortorelli
CPC分类号： G11C13/0033 , G11C13/0004 , G11C13/004 , G11C13/0038 , G11C13/0069 , G11C29/021 , G11C29/12005
摘要： A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.
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公开(公告)号：US20240021257A1
公开(公告)日：2024-01-18
申请号：US18298735
申请日：2023-04-11
申请人： FIDELIX CO., LTD.
发明人： Jae Jin LEE
IPC分类号： G11C29/02
CPC分类号： G11C29/021 , G11C29/026
摘要： An aging monitoring circuit of a semiconductor memory device includes a threshold voltage sensing part including an aging monitoring transistor, enabled in response to activation of an aging monitoring signal, and generating a sensing threshold signal, a level of the sensing threshold signal depending on a threshold voltage of the aging monitoring transistor, a reference threshold storage part receiving the sensing threshold signal generated in response to activation of a reference sensing signal and storing a reference threshold voltage, a level of the reference threshold voltage depending on the level of the sensing threshold signal, and a level comparing part enabled in response to the activation of the aging monitoring signal and generating an aging flag signal, a logic state of the aging flag signal depending on a comparison result between the level of the sensing threshold signal and the level of the reference threshold voltage.
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公开(公告)号：US11869609B2
公开(公告)日：2024-01-09
申请号：US17846009
申请日：2022-06-22
发明人： Xikun Chu
CPC分类号： G11C29/021 , G11C29/54
摘要： Provided are a method for testing a memory, an apparatus for testing a memory, a computer-readable storage medium, and an electronic device, which relate to the field of integrated circuit technology. The method for testing a memory includes: writing first data into each of memory cells of a memory array; enabling a data mask mode, and writing second data into each of the memory cells of the memory array; enabling a leakage mode, and writing the first data into a memory cell corresponding to a column under test of the memory array; and after preset leakage time, disabling the leakage mode, and reading data from the memory cell corresponding to the column under test for testing, to determine whether there are at least two columns simultaneously turned on in the memory array. This method may test whether a row decoder fails.
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