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公开(公告)号：US20240296897A1
公开(公告)日：2024-09-05
申请号：US18660002
申请日：2024-05-09
发明人： Melissa I. Uribe
IPC分类号： G11C29/02 , G11C11/4076 , G11C11/4099 , H03K19/20
CPC分类号： G11C29/022 , G11C11/4076 , G11C11/4099 , G11C29/021 , H03K19/20
摘要： Methods, systems, and devices for techniques for determining an interface connection status are described. A system may include an interface between a host device and a memory device. The host device may transmit to the memory device first data in a pattern over a first set of transmission lines of the interface. The host device may also transmit to the memory device second data in the pattern over a second set of transmission lines of the interface. The memory device may compare the first data and the second data, and based on the comparison, send an indication of a connection status of the interface to the host device.
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公开(公告)号：US12079078B2
公开(公告)日：2024-09-03
申请号：US17820120
申请日：2022-08-16
发明人： Melissa I. Uribe , Steffen Buch
CPC分类号： G06F11/1068 , G06F11/0772 , G06F11/079
摘要： Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of CA bits associated with a command signal or an address signal. The memory device may receive, from the host device via the CA bus, a first set of parity bits that is based on the plurality of CA bits and a select parity generation process. The memory device may generate a second set of parity bits, based on the plurality of CA bits, using the select parity generation process. The memory device may compare the first set of parity bits and the second set of parity bits. The memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.
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公开(公告)号：US20230207039A1
公开(公告)日：2023-06-29
申请号：US17646264
申请日：2021-12-28
发明人： Melissa I. Uribe
CPC分类号： G11C29/42 , G11C29/4401 , G11C7/1039 , G11C7/1096 , G11C7/1069
摘要： Methods, systems, and devices for read command fault detection in a memory system are described. For example, a memory device may be configured to set a field of a register with a first value, corresponding to a state where a read command has not been decoded. If the memory device receives and decodes a read command from a host device, the memory device may set the field with a second value. The memory device indicate a value of the field of the register to the host device, which may be used to evaluate whether to process information interpreted over an interface between the host device and the memory device. For example, if the host device receives an indication of the second value, the host device may proceed with processing and, if the host device receives an indication of the first value, the host device may refrain from processing.
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公开(公告)号：US20230205615A1
公开(公告)日：2023-06-29
申请号：US18068152
申请日：2022-12-19
发明人： Melissa I. Uribe , Aaron P. Boehm
IPC分类号： G06F11/07
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/079
摘要： Methods, systems, and devices for error detection signaling are described. In some examples, a memory device may include circuitry to detect one or more error conditions. As the memory device is operated, it may store or output a value (e.g., a high value, a “1”) indicating the absence of an error condition. Upon the occurrence of an error condition, the memory device may either store or output a value (e.g., a low value, a “0”), which may allow for the error to be corrected or mitigated. Because storing or driving the value signifying the error condition may require a driver of the memory device to be coupled with a power supply, storing or outputting the value signifying an absence of an error condition (e.g., unless a normal or valid condition is detected) may mitigate errors that would otherwise render a safety mechanism of the memory device ineffective.
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公开(公告)号：US12009835B2
公开(公告)日：2024-06-11
申请号：US17814402
申请日：2022-07-22
发明人： Aaron P. Boehm , Melissa I. Uribe
CPC分类号： H03M13/1174 , G11C8/06 , H03M13/098
摘要： Implementations described herein relate to command address fault detection. A memory device may receive, from a host device via a command address (CA) bus, a plurality of bits associated with a command signal or an address signal. The CA bus may be configured for communicating command signals and address signals between the memory device and the host device. The memory device may generate one or more parity bits based on the plurality of bits. The one or more parity bits may be generated using a parity generation process that is common to the memory device and the host device. The memory device may transmit, to the host device, the one or more parity bits.
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公开(公告)号：US11928021B2
公开(公告)日：2024-03-12
申请号：US17711002
申请日：2022-03-31
发明人： Melissa I. Uribe
CPC分类号： G06F11/1016 , G06F11/1044
摘要： A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes an address fault detection system designed to detect a mismatch between the address originally used to store the data and the address subsequently used to read the data. The address fault detection system generates an address parity bit from the received address and either stores that address parity bit with the user data or uses the address parity bit to invert the internal ECC bits generated from the user data. The address fault detection system can determine from the resulting syndrome from the ECC bits whether or not an address fault has occurred and raise an address fault indication flag if the address fault is detected.
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公开(公告)号：US20220137880A1
公开(公告)日：2022-05-05
申请号：US17505046
申请日：2021-10-19
摘要： Methods, systems, and devices for memory bus drive defect detection and related operations are described. A controller coupled with a memory array may receive a command for data. The memory array may include one or more pins for communicating data to and from the memory array, in response to the command. The controller may transmit to the memory array, over a bus that is coupled with the controller and the pins, the command. The controller may detect, based at least in part on a resistor coupled with the bus and a power supply of the memory array, that the bus is operating in a first state after transmitting the command. The first state may comprise a voltage that is relatively higher than a voltage of the second state. The controller may determine a defect associated with the bus or the pin based on detecting the bus in the first state.
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公开(公告)号：US12130702B2
公开(公告)日：2024-10-29
申请号：US17880220
申请日：2022-08-03
发明人： Melissa I. Uribe
CPC分类号： G06F11/1048 , G06F11/1076
摘要： Methods, systems, and devices for memory operations are described. A pin associated with communicating error correction information may be biased, via a first circuit, to a first voltage level by a first voltage source that is coupled with the pin when the pin is in an idle state. Also, a set of data pins may be biased, via a second circuit, to a second voltage level by a second voltage source when the set of data pins is in the idle state. When a memory device misses a command transmitted from a host device, the voltage levels of the pin and set of data pins may remain at the respective voltage levels throughout a period during which the host device executes an operation associated with the missed command, indicating to the host device that data communicated by a corresponding data signal is invalid.
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公开(公告)号：US20240161854A1
公开(公告)日：2024-05-16
申请号：US18423059
申请日：2024-01-25
发明人： Melissa I. Uribe
CPC分类号： G11C29/42 , G11C7/1039 , G11C7/1069 , G11C7/1096 , G11C29/4401
摘要： Methods, systems, and devices for read command fault detection in a memory system are described. For example, a memory device may be configured to set a field of a register with a first value, corresponding to a state where a read command has not been decoded. If the memory device receives and decodes a read command from a host device, the memory device may set the field with a second value. The memory device indicate a value of the field of the register to the host device, which may be used to evaluate whether to process information interpreted over an interface between the host device and the memory device. For example, if the host device receives an indication of the second value, the host device may proceed with processing and, if the host device receives an indication of the first value, the host device may refrain from processing.
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公开(公告)号：US11923027B2
公开(公告)日：2024-03-05
申请号：US17646264
申请日：2021-12-28
发明人： Melissa I. Uribe
CPC分类号： G11C29/42 , G11C7/1039 , G11C7/1069 , G11C7/1096 , G11C29/4401
摘要： Methods, systems, and devices for read command fault detection in a memory system are described. For example, a memory device may be configured to set a field of a register with a first value, corresponding to a state where a read command has not been decoded. If the memory device receives and decodes a read command from a host device, the memory device may set the field with a second value. The memory device indicate a value of the field of the register to the host device, which may be used to evaluate whether to process information interpreted over an interface between the host device and the memory device. For example, if the host device receives an indication of the second value, the host device may proceed with processing and, if the host device receives an indication of the first value, the host device may refrain from processing.
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