公开(公告)号：US20230386577A1

公开(公告)日：2023-11-30

申请号：US17752662

申请日：2022-05-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Ying Lee ,  Chia-En Huang ,  Chieh Lee

IPC分类号： G11C16/08 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/11578

CPC分类号： G11C16/08 ,  G11C16/0483 ,  H01L27/11551 ,  H01L27/11578

摘要： A memory device includes a plurality of word lines (WLs). The memory device includes a plurality of drivers that are each configured to control a corresponding one of the plurality of WLs and each comprise a first transistor having a first conductive type and a second transistor having a second conductive type. The first transistor of a first one of the drivers is formed in a first well of a substrate, and the second transistor of the first driver is formed in a second well of the substrate. The first well is spaced apart from the second well.

公开(公告)号：US20230361030A1

公开(公告)日：2023-11-09

申请号：US17738715

申请日：2022-05-06

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Yuancheng Yang ,  Dongxue Zhao ,  Tao Yang ,  Lei Liu ,  Di Wang ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC分类号： H01L23/528 ,  H01L27/11578 ,  H01L27/11551

CPC分类号： H01L23/5283 ,  H01L27/11578 ,  H01L27/11551

摘要： Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a memory stack on the bottom conductive layer, the memory stack comprising a plurality of alternatively arranged dielectric layers and conductive layers; forming an opening penetrating the memory stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and forming a plurality of interconnection structures to electrically connect the bottom conductive layer, the plurality of conductive layers of the memory stack, and the top contact.

公开(公告)号：US20230200061A1

公开(公告)日：2023-06-22

申请号：US17558001

申请日：2021-12-21

申请人： Intel Corporation

发明人： Li Cheng

IPC分类号： H01L27/11524 ,  H01L27/11551

CPC分类号： H01L27/11524 ,  H01L27/11551 ,  G11C11/4085

摘要： Systems, apparatuses, and methods may provide for technology for forming a pre-offset platform on top of a substrate. A memory block is formed, where the memory block includes a staircase area and a memory array area located adjacent the staircase area. The memory array area includes a plurality of memory pillars extending into the memory block. The staircase area has a first height, the memory array area has a second height, and a tier expansion height is defined as a difference between the second height and the first height. The pre-offset platform is located between the substrate and the staircase area of the memory block. The pre-offset platform is oriented and arranged to offset the tier expansion height so that an upper surface of the staircase area and an upper surface of the memory array area are located in a same plane.

公开(公告)号：US11665892B2

公开(公告)日：2023-05-30

申请号：US16881279

申请日：2020-05-22

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Zhongwang Sun ,  Zhong Zhang ,  Wenxi Zhou ,  Zhiliang Xia

IPC分类号： H01L27/11551 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157

CPC分类号： H01L27/11551 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11578

摘要： Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first and second memory array structures. The bridge structure includes a lower wall portion and an upper staircase portion. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

公开(公告)号：US20230111711A1

公开(公告)日：2023-04-13

申请号：US17514649

申请日：2021-10-29

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Liang Chen ,  Wei Liu

IPC分类号： H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11573

摘要： In certain aspects, a three-dimensional (3D) memory device includes a single crystalline silicon layer, a polysilicon layer, a transistor in contact with the single crystalline silicon layer, and a channel structure in contact with the polysilicon layer. The polysilicon layer and the single crystalline silicon layer are nonoverlapping and at least partially noncoplanar.

公开(公告)号：US11615977B2

公开(公告)日：2023-03-28

申请号：US17945459

申请日：2022-09-15

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

摘要： A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

公开(公告)号：US20230079244A1

公开(公告)日：2023-03-16

申请号：US17949436

申请日：2022-09-21

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC分类号： H01L27/105 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/108 ,  H01L29/24 ,  H01L29/786

摘要： An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

公开(公告)号：US20230067814A1

公开(公告)日：2023-03-02

申请号：US17447505

申请日：2021-09-13

申请人： Micron Technology, Inc.

发明人： Raja Kumar Varma Manthena ,  Paolo Tessariol

IPC分类号： H01L21/768 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

摘要： A method of forming a microelectronic device comprises forming a stack structure over a source structure, forming pillar structures vertically extending through the stack structure, and forming at least one trench vertically extending through the stack structure. The at least one trench defines at least one stadium structure comprising opposing stair step structures having steps comprising horizontal ends of tiers. Additional trenches may be formed to vertically extend through the stack structure, and at least one further trench may be formed to vertically extend through the stack structure. The at least one further trench defines at least one additional stadium structure comprising additional opposing stair step structures having additional steps comprising additional horizontal ends of the tiers. A dielectric material may be formed within the at least one trench, the additional trenches, and the at least one further trench. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20230066649A1

公开(公告)日：2023-03-02

申请号：US17450729

申请日：2021-10-13

申请人： Micron Technology, Inc.

发明人： Erwin E. Yu ,  Surendranath C. Eruvuru ,  Yoshiaki Fukuzumi ,  Tomoko Ogura Iwasaki

IPC分类号： H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  G11C16/24 ,  G11C7/10 ,  B81B7/02

摘要： A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11594549B2

公开(公告)日：2023-02-28

申请号：US17202690

申请日：2021-03-16

申请人： Kioxia Corporation

发明人： Ayumi Watarai ,  Taichi Iwasaki ,  Osamu Matsuura ,  Yu Hirotsu ,  Sota Matsumoto

IPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  G11C8/14 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11551

摘要： A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region.
The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.