公开(公告)号：US11955422B2

公开(公告)日：2024-04-09

申请号：US17488287

申请日：2021-09-28

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Lei Xue ,  Wei Liu ,  Liang Chen

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H10B43/27 ,  H10B43/35

CPC分类号： H01L23/5223 ,  H01L21/76832 ,  H01L28/40 ,  H01L28/56 ,  H10B43/27 ,  H10B43/35

摘要： Embodiments of semiconductor devices and methods for forming the same are disclosed. In an example, a semiconductor device includes at least one dielectric layer pair including a first dielectric layer and a second dielectric layer different from the first dielectric layer, an interlayer dielectric (ILD) layer in contact with the at least one dielectric layer pair, and one or more capacitors each extending vertically through the ILD layer and in contact with the at least one dielectric layer pair.

公开(公告)号：US11721609B2

公开(公告)日：2023-08-08

申请号：US17347086

申请日：2021-06-14

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Liang Chen ,  Wei Liu ,  Shao-Fu Sanford Chu

IPC分类号： H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L23/535

CPC分类号： H01L23/481 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/535

摘要： In a method for forming an integrated structure, a top dielectric layer is formed over a top surface of a substrate. The top dielectric layer includes a plurality of vias that are formed through the top dielectric layer and extend into the substrate. A bottom dielectric layer is formed on a bottom surface of the substrate. An isolation opening and a plurality of contact openings are further formed in the bottom dielectric layer and the substrate, where the isolation opening passes through the bottom dielectric layer and extends from the bottom surface to the top surface of the substrate. The isolation opening is filled with an insulating layer to form an isolation trench. The plurality of contact openings are filled with a conductive layer to form a plurality of through silicon contacts (TSCs). A conductive plate is further formed over the bottom dielectric layer.

公开(公告)号：US11710679B2

公开(公告)日：2023-07-25

申请号：US17338231

申请日：2021-06-03

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Liang Chen ,  Wei Liu ,  Shao-Fu Sanford Chu

IPC分类号： H01L23/48 ,  H01L21/762 ,  H01L21/768 ,  H01L23/535

CPC分类号： H01L23/481 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/535

摘要： In a TSC structure, a first dielectric layer is formed over a first main surface of a substrate. A TSC is formed in the first dielectric layer and the substrate so that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate is formed over the first dielectric layer and electrically coupled with the TSC. A second dielectric layer is formed on an opposing second main surface of the substrate. A first via is formed in the second dielectric layer, and a first end of the first via extends into the substrate to be in contact with the TSC. A second via is formed in the second dielectric layer and a first end of the second via extends into the substrate. A metal line is formed over the second dielectric layer so as to be coupled to the first via and the second via.

公开(公告)号：US20230157027A1

公开(公告)日：2023-05-18

申请号：US17846612

申请日：2022-06-22

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Liang Chen ,  Shiqi Huang ,  Wei Liu ,  Yanhong Wang

IPC分类号： H01L27/11575 ,  H01L27/11582

CPC分类号： H01L27/11575 ,  H01L27/11582

摘要： A three-dimensional (3D) memory device includes a plurality of memory stacks arranged along a first direction, and a dummy block structure disposed between two adjacent memory stacks. Each memory stack includes a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction. A channel structure extends through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction. A first isolation structure is disposed between the dummy block structure and one of the plurality of memory stacks. A substrate is disposed under the plurality of memory stacks, the dummy block structure, and the first isolation structure. A second isolation structure is disposed in the substrate extending along the second direction.

公开(公告)号：US20230048644A1

公开(公告)日：2023-02-16

申请号：US17483086

申请日：2021-09-23

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Liang Chen ,  Wei Liu

IPC分类号： H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11529

摘要： In certain aspects, a semiconductor device includes a substrate, a first trench isolation in the substrate, a second trench isolation in the substrate and surrounding a portion of the substrate, and a first routing electrode layer extending through the first trench isolation. The portion of the substrate is an active region of a transistor.

公开(公告)号：US20230005861A1

公开(公告)日：2023-01-05

申请号：US17481838

申请日：2021-09-22

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Yanhong Wang ,  Wei Liu ,  Liang Chen ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

公开(公告)号：US20230005858A1

公开(公告)日：2023-01-05

申请号：US17480931

申请日：2021-09-21

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Liang Chen ,  Wei Liu ,  Yanhong Wang ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The first peripheral circuit is between the first bonding interface and the second semiconductor layer. The second peripheral circuit is between the second bonding interface and the third semiconductor layer.

公开(公告)号：US20230005856A1

公开(公告)日：2023-01-05

申请号：US17480852

申请日：2021-09-21

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Liang Chen ,  Wei Liu ,  Yanhong Wang ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit of the array of memory cells including a first transistor in contact with a first side of the second semiconductor layer, and a second peripheral circuit of the array of NAND memory strings including a second transistor in contact with a second side of the second semiconductor layer opposite to the first side.

公开(公告)号：US20230005545A1

公开(公告)日：2023-01-05

申请号：US17481902

申请日：2021-09-22

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Yanhong Wang ,  Wei Liu ,  Liang Chen ,  Zhiliang Xia ,  Wenxi Zhou ,  Kun Zhang ,  Yuancheng Yang

IPC分类号： G11C16/10 ,  G11C16/04 ,  H01L23/528 ,  G11C16/26 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

公开(公告)号：US20230005542A1

公开(公告)日：2023-01-05

申请号：US17481020

申请日：2021-09-21

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Kun Zhang ,  Yuancheng Yang ,  Wenxi Zhou ,  Wei Liu ,  Zhiliang Xia ,  Liang Chen ,  Yanhong Wang

IPC分类号： G11C16/04 ,  H01L23/528 ,  H01L23/522 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the first semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The second peripheral circuit is between the second bonding interface and the third semiconductor layer.