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    MEMORY DEVICES AND METHODS FOR FORMING THE SAME
    5.
    发明公开
    MEMORY DEVICES AND METHODS FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20240074156A1

    公开(公告)日：2024-02-29

    申请号：US18237291

    申请日：2023-08-23

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Zichen Liu ,  Wei Liu

    IPC: H10B12/00

    CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/33

    Abstract: A memory device includes an array of memory cells, bit lines coupled to the memory cells, first air gaps, and second air gaps. Each of the memory cells includes a vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction. Each of the bit lines is connected to a first end of the semiconductor body. At least one of the first air gaps is between adjacent bit lines. At least one of the second air gaps is between adjacent semiconductor bodies of adjacent memory cells.

    THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME
    7.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME 有权

    公开(公告)号：US20230110729A1

    公开(公告)日：2023-04-13

    申请号：US17514678

    申请日：2021-10-29

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Liang Chen ,  Wei Liu

    IPC: H01L27/11573 ,  H01L27/11578 ,  H01L27/11531 ,  H01L27/11551

    Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A transistor is formed in a first region on a first side of a single crystalline silicon substrate. A step layer is formed in a second region on the first side of the single crystalline silicon substrate. A channel structure extending through a stack structure and in contact with the step layer is formed. The stack structure includes interleaved dielectric layers and conductive layers on the step layer. Part of the single crystalline silicon substrate that is in the second region is removed from a second side opposite to the first side of the single crystalline silicon substrate to expose the step layer from the second side.

    MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME
    8.
    发明申请
    MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME 有权

    公开(公告)号：US20230062141A1

    公开(公告)日：2023-03-02

    申请号：US17553759

    申请日：2021-12-16

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Hongbin Zhu ,  Wei Liu ,  Yanhong Wang

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: In certain aspects, a memory device includes a memory cell including a vertical transistor, and a storage unit having a first end coupled to a first terminal of the vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The memory device also includes a metal bit line coupled to a second terminal of the vertical transistor via an ohmic contact and extending in a second direction perpendicular to the first direction. The memory device further includes a dielectric layer opposing the memory cell with the metal bit line positioned between the dielectric layer and the memory cell. The memory device further includes a conductor extending from the dielectric layer to couple to a second end of the storage unit.

    MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME
    9.
    发明申请
    MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME 有权

    公开(公告)号：US20230060149A1

    公开(公告)日：2023-03-02

    申请号：US17553781

    申请日：2021-12-16

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Hongbin Zhu ,  Wei Liu ,  Yanhong Wang ,  Ning Jiang

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

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