公开(公告)号：US20240422959A1

公开(公告)日：2024-12-19

申请号：US18473904

申请日：2023-09-25

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Yaqin Liu ,  Wei Liu ,  Liang Chen ,  Zichen Liu ,  Yanhong Wang

IPC: H10B12/00

Abstract: A semiconductor structure and a fabrication method thereof, a memory and a memory system are provided. The method includes: forming a plurality of capacitor holes penetrating through a first stack layer comprising a first region and a second region where the capacitor holes are located; forming a first electrode layer on inner walls of the capacitor holes; forming a dielectric layer in the first region and the second region; forming a second electrode layer on a side of the dielectric layer; removing the second electrode layer on the first stack layer in the second region; and forming a contact structure penetrating through the first stack layer in the second region. The method can prevent an etch loading effect from occurring in the first region during formation of the capacitor holes, which is favorable to form capacitor structures with a uniform size, thus improving reliability of the capacitor structures.

公开(公告)号：US20240023320A1

公开(公告)日：2024-01-18

申请号：US18219570

申请日：2023-07-07

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yaqin Liu ,  Yanhong Wang ,  Wei Liu

IPC: H10B12/00 ,  H10B63/10 ,  H10B63/00

CPC classification number: H10B12/485 ,  H10B63/10 ,  H10B63/34 ,  H10B63/84 ,  H10B12/50 ,  H10B12/05 ,  H10B12/03

Abstract: A memory device includes a memory array structure including a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor, a first peripheral circuit coupled to a first surface of the memory array structure, and a second peripheral circuit coupled to a second surface of the memory array structure opposite to the first surface. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body.

公开(公告)号：US20240057325A1

公开(公告)日：2024-02-15

申请号：US18231742

申请日：2023-08-08

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yanhong Wang ,  Wei Liu ,  Yaqin Liu ,  Shiqi Huang ,  Liang Chen

IPC: H10B12/00 ,  G11C11/408 ,  G11C11/4091 ,  H10B63/10

CPC classification number: H10B12/50 ,  H10B12/485 ,  H10B12/09 ,  H10B12/05 ,  H10B12/03 ,  H10B12/315 ,  G11C11/4085 ,  G11C11/4091 ,  H10B63/10

Abstract: A memory device includes a memory array structure, a first peripheral circuit, and a second peripheral circuit. The memory array structure includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The first peripheral circuit is disposed at one side of the memory array structure and includes a first side in contact with the memory array structure and a second side opposite to the first side in a first direction. The second peripheral circuit is disposed in contact with the second side of the first peripheral circuit away from the memory array structure.

公开(公告)号：US20240389296A1

公开(公告)日：2024-11-21

申请号：US18372579

申请日：2023-09-25

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Liang Chen ,  Zichen Liu ,  Yanhong Wang ,  Yaqin Liu ,  Wei Liu

IPC: H10B12/00

Abstract: A semiconductor structure, a fabrication method thereof, a memory, and a memory system are provided. The method may include forming a plurality of capacitor holes extending through a stack of layers in the first region and the second region of the stack of layers. The method may include forming a first electrode layer over the inside walls of the respective capacitor holes. The method may include forming a dielectric layer over the stack of layers. The method may include removing at least part of the dielectric layer in the second region. The method may include forming a second electrode layer. The portion of the second electrode layer in the first region may be separated from the portion of the second electrode layer in the second region. In the second region, the first electrode layer may be connected with the second electrode layer.

公开(公告)号：US20240098973A1

公开(公告)日：2024-03-21

申请号：US18231731

申请日：2023-08-08

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yaqin Liu ,  Wei Liu ,  Yanhong Wang ,  Shiqi Huang ,  Zichen Liu

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor device, a memory system, and a fabricating method are provided. The semiconductor device comprises a memory structure bonded with a circuit structure. The memory structure comprises: first transistors each comprising a semiconductor body extending in a vertical direction, a semiconductor layer on a lateral side of the first transistors, a first isolation structure extending through the semiconductor layer and laterally encircling a first portion of the semiconductor layer, a first contact structure extending through the first portion of the semiconductor layer, and a first contact pad above the first portion of the semiconductor layer and connected with the first contact structure. A lateral dimension of the first contact pad is less than a lateral dimension of the first portion of the semiconductor layer. The circuit structure comprises a second transistor, and the first contact pad is electrically connected to the second transistor by the first contact structure.

公开(公告)号：US20230413531A1

公开(公告)日：2023-12-21

申请号：US18220096

申请日：2023-07-10

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Yaqin Liu ,  Yanhong Wang ,  Wei Liu

IPC: H10B12/00 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B12/33 ,  H10B12/482 ,  H10B12/036 ,  H10B12/05 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The vertical transistor is disposed between the bit line and the storage unit along the first direction.