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公开(公告)号：US20240365567A1
公开(公告)日：2024-10-31
申请号：US18471585
申请日：2023-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinwoo Lee , Dongho Ahn , Jin Myung Choi
IPC: H10B63/00
CPC classification number: H10B63/845 , H10B63/34
Abstract: A semiconductor device according to an embodiment includes a gate stack structure and a channel structure. The gate stack structure includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked on a substrate in a first direction perpendicular to an upper surface of the substrate. The channel structure includes a portion penetrating through the gate stack structure and extending in the first direction. The channel structure includes a channel layer, a resistance change layer, and a metal-containing layer sequentially stacked. The metal-containing layer includes a metal or a metal compound.
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公开(公告)号：US20240357838A1
公开(公告)日：2024-10-24
申请号：US18763239
申请日：2024-07-03
Inventor： Chao-I Wu , Yu-Ming Lin
CPC classification number: H10B63/845 , H10B63/34 , H10N70/066
Abstract: A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.
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公开(公告)号：US12101935B2
公开(公告)日：2024-09-24
申请号：US17408149
申请日：2021-08-20
Applicant: SK hynix Inc.
Inventor： Seo Hyun Kim , In Ku Kang
Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure with first material layers and second material layers that are alternately stacked with each other, forming a first opening that passes through the stacked structure, forming second openings between the first material layers, forming first sacrificial layers in the second openings, forming first isolation layers that protrude into the first opening by oxidizing the first sacrificial layers, forming mold patterns on the first material layers between the protruding portions of the first isolation layers, forming third openings by etching portions of the first isolation layers that are exposed between the mold patterns, forming second sacrificial layers in the third openings, and forming second isolation layers that protrude farther toward the center of the first opening than the mold patterns by oxidizing the second sacrificial layers.
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公开(公告)号：US12069872B2
公开(公告)日：2024-08-20
申请号：US18231304
申请日：2023-08-08
Applicant: Kioxia Corporation
Inventor： Takahiko Iizuka , Daisaburo Takashima , Ryu Ogiwara , Rieko Funatsuki , Yoshiki Kamata , Misako Morota , Yoshiaki Asao , Yukihiro Nomura
CPC classification number: H10B63/845 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C13/0069 , H10B63/34 , H10N70/066 , H10N70/231 , H10N70/8828 , G11C2213/75
Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
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公开(公告)号：US20240164225A1
公开(公告)日：2024-05-16
申请号：US18173815
申请日：2023-02-24
Inventor： Jheng-Hong Jiang , Chung-Liang Cheng
CPC classification number: H10N70/8418 , H10B63/34 , H10N70/063 , H10N70/883
Abstract: A resistive random access memory (RRAM) device is provided. The RRAM includes: a bottom electrode via disposed in a first dielectric layer; a bottom electrode electrically connected to the bottom electrode via and protruding upwardly from the bottom electrode via in a vertical direction, wherein the bottom electrode has a tapered shape and includes a base portion extending upwardly from a bottom surface to an interface and a tip portion extending upwardly from the interface to a top surface; a top electrode disposed in a second dielectric layer, the top electrode distanced above and vertically aligned with the bottom electrode; and a switching layer disposed between the first dielectric layer and the second dielectric layer, the switching layer enclosing the bottom electrode, wherein a conductive path between the bottom electrode and the top electrode is formed when a forming voltage is applied.
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Patent Agency Ranking
公开(公告)号：US11985834B2
公开(公告)日：2024-05-14
申请号：US17346478
申请日：2021-06-14
Applicant: Kioxia Corporation
Inventor： Yoshiki Kamata , Misako Morota , Yukihiro Nomura , Yoshiaki Asao
CPC classification number: H10B63/845 , H10B53/20 , H10B53/30 , H10B63/34
Abstract: A semiconductor memory device, includes: a stack including a wiring layer and an insulation layer alternately stacked in a first direction; a semiconductor layer including a first region overlapping with the insulation layer in a second direction, and a second region overlapping with the wiring layer in the second direction; an insulation region between the wiring layer and the second region; and a memory region on the opposite side of the second region from the wiring layer. The wiring layer is farther from the first region in the second direction than the insulation layer is. The second region has a part between the insulation layers in the first direction and protruding further toward the wiring layer than the first region in the second direction. The memory region has a face opposite to the second region and closer to the wiring layer in the second direction than the first region is.
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公开(公告)号：US20240155848A1
公开(公告)日：2024-05-09
申请号：US18414135
申请日：2024-01-16
Applicant: Zeno Semiconductor, Inc.
Inventor： Jin-Woo Han , Yuniarto Widjaja
Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.
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公开(公告)号：US20240147738A1
公开(公告)日：2024-05-02
申请号：US18404103
申请日：2024-01-04
Inventor： Chao-I Wu , Yu-Ming Lin
CPC classification number: H10B63/34 , G11C7/18 , G11C8/14 , H01L23/5226 , H01L29/78391 , H10N70/061 , H10N70/253 , H10N70/8265 , H10N70/841
Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.
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公开(公告)号：US11943930B2
公开(公告)日：2024-03-26
申请号：US18334583
申请日：2023-06-14
Applicant: SK hynix Inc.
Inventor： Dong Uk Lee , Hae Chang Yang
CPC classification number: H10B43/27 , G11C13/0004 , G11C13/0069 , G11C16/0483 , G11C16/10 , H10B41/27 , H10B63/34 , H10B63/845 , H10N70/231 , G11C2213/75
Abstract: A semiconductor memory device and methods of manufacturing and operating the same are set forth. The semiconductor memory device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, which may be alternately stacked on a substrate, and a plurality of channel structures penetrating the stack structure in a vertical direction. Each of the plurality of channel structures includes a channel layer, a tunnel insulating layer, an emission preventing layer, and a charge storage layer, each of which vertically extends toward the substrate.
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公开(公告)号：US11895849B2
公开(公告)日：2024-02-06
申请号：US17882845
申请日：2022-08-08
Inventor： Chao-I Wu , Yu-Ming Lin
IPC: H01L27/24 , H01L45/00 , H10B63/00 , H01L29/78 , H01L23/522 , G11C7/18 , G11C8/14 , H10N70/00 , H10N70/20
CPC classification number: H10B63/34 , G11C7/18 , G11C8/14 , H01L23/5226 , H01L29/78391 , H10N70/061 , H10N70/253 , H10N70/8265 , H10N70/841
Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.
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