公开(公告)号：US20240334682A1

公开(公告)日：2024-10-03

申请号：US18522932

申请日：2023-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Won YOO ,  Seok Han PARK ,  Ki Seok LEE ,  Hyun Geun CHOI ,  Jin Woo HAN

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/09 ,  H10B12/33 ,  H10B12/50

Abstract: A semiconductor memory device with improved integration and electrical characteristics. The semiconductor memory device includes a peri-gate structure, a first peri-connecting structure on the peri-gate structure, a data storage pattern on the first peri-connecting structure, an active pattern that includes a first surface and a second surface opposite to each other in a first direction, and a first side wall and a second side wall opposite to each other in a second direction, the first surface of the active pattern connected to the data storage pattern and facing a substrate, a bit line on the active pattern, connected to the second surface of the active pattern, and extends in the second direction, a word line on the first side wall of the active pattern and extending in a third direction, a second peri-connecting structure connected to the bit line and a connecting pad connected to the second peri-connecting wiring.

公开(公告)号：US20240324172A1

公开(公告)日：2024-09-26

申请号：US18612672

申请日：2024-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon KWON ,  Yanghee Lee

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/0335

Abstract: A method of manufacturing a semiconductor device includes preparing a substrate including a plurality of active regions and a peripheral active region defined by an isolation layer, forming a word line in a word line trench that crosses the plurality of active regions, forming a plurality of bit line structures, each of the plurality of bit line structures including a bit line on the plurality of active regions, forming a plurality of gate line structures, each of the plurality of gate line structures including a gate line on the peripheral active region, forming a plurality of buried contacts between the plurality of bit line structures, the plurality of buried contacts being connected to the plurality of active regions, and forming an inter-gate insulating layer between the plurality of gate line structures, the inter-gate insulating layer including an oxide having impurities.

公开(公告)号：US12100440B2

公开(公告)日：2024-09-24

申请号：US17828273

申请日：2022-05-31

Applicant: Changxin Memory Technologies, Inc.

Inventor： Qinghua Han

IPC: G11C11/40 ,  G11C11/4091 ,  H10B12/00

CPC classification number: G11C11/4091 ,  H10B12/09

Abstract: The invention provides a sense amplifier circuit, a method for operating same, and a fabrication method for same. The sense amplifier circuit includes: an amplifier electrically connected to a memory cell of a semiconductor memory; and a pre-amplifier located between the amplifier and the memory cell, where the pre-amplifier is configured to pre-amplify an electrical signal transmitted from the memory cell to the amplifier. In this way, the pre-amplifier is provided between the amplifier and the memory cell, such that the electrical signal stored in the semiconductor memory can be output after two stages of amplification by the pre-amplifier and the amplifier, thereby avoiding the problem that the electrical signal output from the memory cell cannot be accurately received and output in a case of a small sense margin of a signal of the sense amplifier.

公开(公告)号：US12089394B2

公开(公告)日：2024-09-10

申请号：US17947172

申请日：2022-09-19

Applicant: Winbond Electronics Corp.

Inventor： Chi-An Wang ,  Kai Jen ,  Wei-Che Chang

IPC: H01L23/522 ,  H10B12/00

CPC classification number: H10B12/09 ,  H10B12/0335 ,  H10B12/31 ,  H10B12/50

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate having a capacitor region and a periphery region and a capacitor. A transistor is disposed in the substrate in the capacitor region, and a conductive device is disposed in the substrate in the periphery region. The capacitor is disposed on the substrate in the capacitor region and electrically connected to the transistor, wherein an upper electrode layer of the capacitor does not extend into the periphery region.

公开(公告)号：US20240206157A1

公开(公告)日：2024-06-20

申请号：US18592121

申请日：2024-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyejin Seong ,  Dongsoo Woo ,  Wonchul Lee

IPC: H10B12/00

CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485 ,  H10B12/50

Abstract: A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug.

公开(公告)号：US20240188278A1

公开(公告)日：2024-06-06

申请号：US18442116

申请日：2024-02-15

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yukihiro Nagai

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/50

Abstract: A method for forming a semiconductor structure for a memory device, including providing a substrate comprising a memory cell region and a peripheral circuit region defined thereon, and the peripheral circuit region comprising at least an active region formed therein, forming at least a buried gate structure in the active region, and an insulating layer being formed on a top of the buried gate structure, and forming a conductive line structure on the buried gate structure, and the conductive line structure and the buried gate structure being physically spaced apart and electrically isolated from each other by the insulating layer.

公开(公告)号：US20240188276A1

公开(公告)日：2024-06-06

申请号：US17782791

申请日：2021-08-06

Applicant: ICLEAGUE TECHNOLOGY CO., LTD.

Inventor： Wenyu HUA ,  Fandong LIU ,  Xiao DING

IPC: H10B12/00 ,  G11C11/4091

CPC classification number: H10B12/09 ,  H10B12/315 ,  H10B12/50 ,  G11C11/4091

Abstract: Embodiments of the disclosure provide a method for manufacturing a memory device, the method includes operations. At least one cell block is formed on a wafer, each of the at least one cell block includes multiple memory cells distributed in an array, each of the multiple memory cells includes a transistor and a storage capacitor connected to a source of the transistor. Bit lines are formed on the wafer, and each of the bit lines is connected to a drain of the transistor, here each of the bit lines and the storage capacitor are located on opposite surfaces of the wafer in a thickness direction respectively. A peripheral circuit is formed above the bit lines on the wafer along a perpendicular of the wafer, here the peripheral circuit includes at least a Sensing Amplifier (SA). An electrical connection is formed between the bit line and the SA.

公开(公告)号：US20240179885A1

公开(公告)日：2024-05-30

申请号：US18495266

申请日：2023-10-26

Applicant: SEMES CO., LTD.

Inventor： Thomas Jongwan KWON ,  Hae Won CHOI ,  Yun Sang KIM ,  Chengyeh HSU

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/09 ,  H10B12/34

Abstract: A method of fabricating a semiconductor device, which is capable of sufficiently filling trenches, is provided. The method includes: providing a substrate having defined thereon a plurality of active regions, which are spaced apart from one another by a device isolation film; forming a plurality of wordline trenches, which extend longitudinally in one direction, by removing portions of the active regions and portions of the device isolation film; forming gate insulating films along inner sidewalls of the wordline trenches; and forming wordlines, which fill portions of the wordline trenches, on the gate insulating films, wherein the forming the wordlines, comprises filling the portions of the wordline trenches with metal layers using a supercritical fluid deposition (SFD) method.

公开(公告)号：US20240178040A1

公开(公告)日：2024-05-30

申请号：US18389577

申请日：2023-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/20 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, second transistors comprise gate electrodes comprising metal, and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.

公开(公告)号：US20240172428A1

公开(公告)日：2024-05-23

申请号：US18518293

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： KYUNGHWAN KIM ,  Hyungeun Choi ,  Keunnam Kim ,  Seokhan Park ,  Seokho Shin ,  Joongchan Shin ,  Kiseok Lee ,  Sangho Lee ,  Moonyoung Jeong

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315

Abstract: A semiconductor device is provided. The semiconductor device includes: a lower structure including a bit line; a cell semiconductor body vertically overlapping the bit line, on the lower structure; a peripheral semiconductor body including a portion disposed on a same level as at least a portion of the cell semiconductor body, on the lower structure; and a peripheral gate on the peripheral semiconductor body, wherein the peripheral semiconductor body includes a lower region having a first width and an upper region having a second width, greater than the first width on the lower region.