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公开(公告)号:US20240074155A1
公开(公告)日:2024-02-29
申请号:US18236143
申请日:2023-08-21
发明人: Taehyuk Kim , Taegyu Kang , Seokho Shin , Kiseok Lee , Sangho Lee , Keunnam Kim , Seokhan Park , Joongchan Shin , Moonyoung Jeong , Eunju Cho
IPC分类号: H10B12/00
CPC分类号: H10B12/482 , H10B12/315 , H10B12/488
摘要: A semiconductor device includes a substrate, a bit line extending on the substrate in a first direction, first and second active patterns on the bit line, a back-gate electrode between the first and second active patterns and extending across the bit line and in a second direction that is perpendicular to the first direction, a first word line extending in the second direction at one side of the first active pattern, a second word line extending in the second direction at the other side of the second active pattern, and a contact pattern connected to each of the first and second active patterns, wherein the contact pattern sequentially includes an epitaxial growth layer, a doped polysilicon layer, and a silicide layer.
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公开(公告)号:US20240172428A1
公开(公告)日:2024-05-23
申请号:US18518293
申请日:2023-11-22
发明人: KYUNGHWAN KIM , Hyungeun Choi , Keunnam Kim , Seokhan Park , Seokho Shin , Joongchan Shin , Kiseok Lee , Sangho Lee , Moonyoung Jeong
IPC分类号: H10B12/00
CPC分类号: H10B12/50 , H10B12/09 , H10B12/315
摘要: A semiconductor device is provided. The semiconductor device includes: a lower structure including a bit line; a cell semiconductor body vertically overlapping the bit line, on the lower structure; a peripheral semiconductor body including a portion disposed on a same level as at least a portion of the cell semiconductor body, on the lower structure; and a peripheral gate on the peripheral semiconductor body, wherein the peripheral semiconductor body includes a lower region having a first width and an upper region having a second width, greater than the first width on the lower region.
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公开(公告)号:US11075183B2
公开(公告)日:2021-07-27
申请号:US16455788
申请日:2019-06-28
发明人: Ju-Ik Lee , Dong-Wan Kim , Seokho Shin , Jung-Hoon Han , Sang-Oh Park
IPC分类号: H01L23/48 , H01L23/00 , H01L25/18 , H01L23/528 , H01L23/31 , H01L23/522
摘要: A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.
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公开(公告)号:US20240170574A1
公开(公告)日:2024-05-23
申请号:US18518264
申请日:2023-11-22
发明人: Joongchan Shin , Kiseok Lee , Seokhan Park , Seokho Shin
CPC分类号: H01L29/7827 , H10B12/0335 , H10B12/482 , H10B12/50
摘要: A semiconductor device includes a vertical channel transistor including a vertical channel region extending in a vertical direction and a cell gate electrode facing a first side surface of the vertical channel region. A bit line is electrically connected to the vertical channel transistor at a level that is lower than a level of the vertical channel transistor. A peripheral semiconductor body has at least a portion thereof disposed on a same level as the vertical channel region. Peripheral source/drain regions are disposed in the peripheral semiconductor body and are spaced apart from each other in a horizontal direction. A peripheral channel region is disposed between the peripheral source/drain regions in the peripheral semiconductor body. A peripheral gate is disposed below the peripheral semiconductor body. At least a portion of the peripheral gate is disposed on a same level as at least a portion of the bit line.
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公开(公告)号:US11764180B2
公开(公告)日:2023-09-19
申请号:US17371405
申请日:2021-07-09
发明人: Ju-Ik Lee , Dong-Wan Kim , Seokho Shin , Jung-Hoon Han , Sang-Oh Park
IPC分类号: H01L23/48 , H01L23/00 , H01L25/18 , H01L23/528 , H01L23/31 , H01L23/522
CPC分类号: H01L24/17 , H01L23/3171 , H01L23/481 , H01L23/5226 , H01L23/5283 , H01L24/09 , H01L25/18 , H01L2224/0401 , H01L2924/1436
摘要: A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.
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公开(公告)号:US11653490B2
公开(公告)日:2023-05-16
申请号:US17471778
申请日:2021-09-10
发明人: Seokho Shin , Taegyu Kang , Byeungmoo Kang , Joongchan Shin
IPC分类号: H01L27/108
CPC分类号: H01L27/10805 , H01L27/1085 , H01L27/10873
摘要: A semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.
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