公开(公告)号：US11289488B2

公开(公告)日：2022-03-29

申请号：US16744572

申请日：2020-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongchan Shin ,  Jiyoung Kim ,  Hui-Jung Kim ,  Taehyun An ,  Eunju Cho ,  Hyungeun Choi ,  Sangyeon Han

IPC: H01L27/108 ,  G11C5/06

Abstract: Disclosed is a semiconductor memory device including a stack structure including layers which are vertically stacked on a substrate and each of which includes a bit line extending in a first direction and a semiconductor pattern extending in a second direction from the bit line, a gate electrode which is in a hole penetrating the stack structure and extending along a stack of semiconductor patterns, a vertical insulating layer covering the gate electrode and filling the hole, and a data storage element electrically connected to the semiconductor pattern. The data storage element includes a first electrode, which is in a first recess of the vertical insulating layer and has a cylindrical shape whose one end is opened, and a second electrode, which includes a first protrusion in a cylinder of the first electrode and a second protrusion in a second recess of the vertical insulating layer.

公开(公告)号：US20240074155A1

公开(公告)日：2024-02-29

申请号：US18236143

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyuk Kim ,  Taegyu Kang ,  Seokho Shin ,  Kiseok Lee ,  Sangho Lee ,  Keunnam Kim ,  Seokhan Park ,  Joongchan Shin ,  Moonyoung Jeong ,  Eunju Cho

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device includes a substrate, a bit line extending on the substrate in a first direction, first and second active patterns on the bit line, a back-gate electrode between the first and second active patterns and extending across the bit line and in a second direction that is perpendicular to the first direction, a first word line extending in the second direction at one side of the first active pattern, a second word line extending in the second direction at the other side of the second active pattern, and a contact pattern connected to each of the first and second active patterns, wherein the contact pattern sequentially includes an epitaxial growth layer, a doped polysilicon layer, and a silicide layer.

公开(公告)号：US11502084B2

公开(公告)日：2022-11-15

申请号：US16986367

申请日：2020-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Changkyu Kim ,  Hui-Jung Kim ,  Iljae Shin ,  Taehyun An ,  Kiseok Lee ,  Eunju Cho ,  Hyungeun Choi ,  Sung-Min Park ,  Ahram Lee ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L21/822

Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.