公开(公告)号：US20240172428A1

公开(公告)日：2024-05-23

申请号：US18518293

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： KYUNGHWAN KIM ,  Hyungeun Choi ,  Keunnam Kim ,  Seokhan Park ,  Seokho Shin ,  Joongchan Shin ,  Kiseok Lee ,  Sangho Lee ,  Moonyoung Jeong

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315

Abstract: A semiconductor device is provided. The semiconductor device includes: a lower structure including a bit line; a cell semiconductor body vertically overlapping the bit line, on the lower structure; a peripheral semiconductor body including a portion disposed on a same level as at least a portion of the cell semiconductor body, on the lower structure; and a peripheral gate on the peripheral semiconductor body, wherein the peripheral semiconductor body includes a lower region having a first width and an upper region having a second width, greater than the first width on the lower region.

公开(公告)号：US20250098153A1

公开(公告)日：2025-03-20

申请号：US18657892

申请日：2024-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taegyu Kang ,  Joongchan Shin ,  Keunui Kim ,  Myeongseon Kim ,  Eunsuk Jang

IPC: H10B12/00

Abstract: A semiconductor device includes: a bit line on a substrate and extending in a first direction; a first word line on the bit line extending in a second direction crossing the first direction; a second word line extending in the second direction on the bit line and spaced from the first word line; first activating patterns on the bit line between the first and second word lines; second activating patterns on the bit line between the first and second word lines; a back gate electrode crossing the bit line and extending in the second direction between the first and second activating patterns; and first and second back gate capping patterns overlapping the back gate electrode. The first back gate capping pattern defines a gap region on the back gate electrode not overlapping the first and second activating patterns, and the second back gate capping pattern is in the gap region.

公开(公告)号：US20240170574A1

公开(公告)日：2024-05-23

申请号：US18518264

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Kiseok Lee ,  Seokhan Park ,  Seokho Shin

IPC: H01L29/78 ,  H10B12/00

CPC classification number: H01L29/7827 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor device includes a vertical channel transistor including a vertical channel region extending in a vertical direction and a cell gate electrode facing a first side surface of the vertical channel region. A bit line is electrically connected to the vertical channel transistor at a level that is lower than a level of the vertical channel transistor. A peripheral semiconductor body has at least a portion thereof disposed on a same level as the vertical channel region. Peripheral source/drain regions are disposed in the peripheral semiconductor body and are spaced apart from each other in a horizontal direction. A peripheral channel region is disposed between the peripheral source/drain regions in the peripheral semiconductor body. A peripheral gate is disposed below the peripheral semiconductor body. At least a portion of the peripheral gate is disposed on a same level as at least a portion of the bit line.

公开(公告)号：US11653490B2

公开(公告)日：2023-05-16

申请号：US17471778

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokho Shin ,  Taegyu Kang ,  Byeungmoo Kang ,  Joongchan Shin

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873

Abstract: A semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.

公开(公告)号：US11289488B2

公开(公告)日：2022-03-29

申请号：US16744572

申请日：2020-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongchan Shin ,  Jiyoung Kim ,  Hui-Jung Kim ,  Taehyun An ,  Eunju Cho ,  Hyungeun Choi ,  Sangyeon Han

IPC: H01L27/108 ,  G11C5/06

Abstract: Disclosed is a semiconductor memory device including a stack structure including layers which are vertically stacked on a substrate and each of which includes a bit line extending in a first direction and a semiconductor pattern extending in a second direction from the bit line, a gate electrode which is in a hole penetrating the stack structure and extending along a stack of semiconductor patterns, a vertical insulating layer covering the gate electrode and filling the hole, and a data storage element electrically connected to the semiconductor pattern. The data storage element includes a first electrode, which is in a first recess of the vertical insulating layer and has a cylindrical shape whose one end is opened, and a second electrode, which includes a first protrusion in a cylinder of the first electrode and a second protrusion in a second recess of the vertical insulating layer.

公开(公告)号：US12156401B2

公开(公告)日：2024-11-26

申请号：US17477634

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Byeungmoo Kang ,  Sangyeon Han

IPC: H10B41/27 ,  G11C5/06 ,  H01L23/538 ,  H10B43/27

Abstract: A three-dimensional (3D) semiconductor memory device including: stack structures spaced apart from each other on a semiconductor substrate, wherein each of the stack structures includes interlayer insulating layers and semiconductor patterns alternately stacked on the semiconductor substrate; conductive patterns provided between the interlayer insulating layers vertically adjacent to each other and connected to the semiconductor patterns; and a protective structure covering a top surface of the semiconductor substrate between the stack structures, wherein a top surface of the protective structure is located between a top surface and a bottom surface of a lowermost interlayer insulating layer of the interlayer insulating layers.

公开(公告)号：US20240074155A1

公开(公告)日：2024-02-29

申请号：US18236143

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyuk Kim ,  Taegyu Kang ,  Seokho Shin ,  Kiseok Lee ,  Sangho Lee ,  Keunnam Kim ,  Seokhan Park ,  Joongchan Shin ,  Moonyoung Jeong ,  Eunju Cho

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device includes a substrate, a bit line extending on the substrate in a first direction, first and second active patterns on the bit line, a back-gate electrode between the first and second active patterns and extending across the bit line and in a second direction that is perpendicular to the first direction, a first word line extending in the second direction at one side of the first active pattern, a second word line extending in the second direction at the other side of the second active pattern, and a contact pattern connected to each of the first and second active patterns, wherein the contact pattern sequentially includes an epitaxial growth layer, a doped polysilicon layer, and a silicide layer.

公开(公告)号：US11751378B2

公开(公告)日：2023-09-05

申请号：US17369320

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun Choi ,  Kiseok Lee ,  Seungjae Jung ,  Joongchan Shin ,  Taehyun An ,  Moonyoung Jeong ,  Sangyeon Han

IPC: H10B12/00 ,  H01L29/08

CPC classification number: H10B12/30 ,  H01L29/0847 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

公开(公告)号：US11502084B2

公开(公告)日：2022-11-15

申请号：US16986367

申请日：2020-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Changkyu Kim ,  Hui-Jung Kim ,  Iljae Shin ,  Taehyun An ,  Kiseok Lee ,  Eunju Cho ,  Hyungeun Choi ,  Sung-Min Park ,  Ahram Lee ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L21/822

Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

公开(公告)号：US20220093626A1

公开(公告)日：2022-03-24

申请号：US17477634

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Byeungmoo Kang ,  Sangyeon Han

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/538

Abstract: A three-dimensional (3D) semiconductor memory device including: stack structures spaced apart from each other on a semiconductor substrate, wherein each of the stack structures includes interlayer insulating layers and semiconductor patterns alternately stacked on the semiconductor substrate; conductive patterns provided between the interlayer insulating layers vertically adjacent to each other and connected to the semiconductor patterns; and a protective structure covering a top surface of the semiconductor substrate between the stack structures, wherein a top surface of the protective structure is located between a top surface and a bottom surface of a lowermost interlayer insulating layer of the interlayer insulating layers.